Florent de Dinechin

92 papers A 5B 11C 20Misc 4Journal 26Unranked 22

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Double-Word Decomposition in a Combined FP16, BF16 and FP32 Dot Product Add Operator. ARITH Orégane Desrentes, Benoît Dupont de Dinechin, Florent de Dinechin
2025	C	`conf`	Hardware Fixed-Point 2D and 3D norms. ARITH Romain Bouarah, Florent de Dinechin
2025	—	`conf`	RETROSPECTIVE: Table-Based Polynomials for Fast Hardware Function Evaluation. ASAP Florent de Dinechin
2025	J	`jnl`	Towards Optimized Arithmetic Circuits with MLIR. WiPiEC Journal Louis Ledoux, Pierre Cochard, Florent de Dinechin
2025	C	`conf`	Towards optimal reconfigurable constant multipliers. DSD Bastien Barbe, Xiao Peng, Anastasia Volkova, Florent de Dinechin
2024	J	`jnl`	Towards Fixed-Point Formats Determination for Faust Programs. CoRR Agathe Herrou, Florent de Dinechin, Stéphane Letz, Yann Orlarey, Anastasia Volkova
2023	—	`conf`	Audio DSP to FPGA Compilation. ASAP Maxime Popoff, Romain Michon, Tanguy Risset, Pierre Cochard, Stéphane Letz, Yann Orlarey, Florent de Dinechin
2023	C	`conf`	Exact Fused Dot Product Add Operators. ARITH Orégane Desrentes, Benoît Dupont de Dinechin, Florent de Dinechin
2023	Misc	`conf`	Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them. ACSSC Anastasia Volkova, Rémi Garcia, Florent de Dinechin, Martin Kumm
2022	—	`conf`	A single-source C++20 HLS flow for function evaluation on FPGA and beyond. HEART Luc Forget, Gauthier Harnisch, Ronan Keryell, Florent de Dinechin
2022	J	`jnl`	Computer Arithmetic: Continuing a Long and Steady Emergence. Computer Paolo Montuschi, Jean-Michel Muller, Florent de Dinechin
2022	J	`jnl`	Lossless Differential Table Compression for Hardware Function Evaluation. IEEE Trans. Circuits Syst. II Express Briefs Maxime Christ, Luc Forget, Florent de Dinechin
2022	—	`conf`	Low-precision logarithmic arithmetic for neural network accelerators. ASAP Maxime Christ, Florent de Dinechin, Frédéric Pétrot
2022	B	`conf`	Resource Optimal Squarers for FPGAs. FPL Andreas Böttcher, Martin Kumm, Florent de Dinechin
2022	—	`conf`	Using integer linear programming for correctly rounded multipartite architectures. FPT Orégane Desrentes, Florent de Dinechin
2021	C	`conf`	Resource Optimal Truncated Multipliers for FPGAs. ARITH Andreas Böttcher, Martin Kumm, Florent de Dinechin
2021	C	`conf`	Towards Arithmetic-Centered Filter Design. ARITH Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Anastasia Volkova
2020	J	`jnl`	Application-Specific Arithmetic in High-Level Synthesis Tools. ACM Trans. Archit. Code Optim. Yohann Uguen, Florent de Dinechin, Victor Lezaud, Steven Derrien
2020	A	`conf`	Next Generation Arithmetic for Edge Computing. DATE Andre Guntoro, Cecilia De la Parra, Farhad Merchant, Florent de Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers, Sangeeth Nambiar
2019	—	`conf`	A type-safe arbitrary precision arithmetic portability layer for HLS tools. HEART Luc Forget, Yohann Uguen, Florent de Dinechin, David Thomas
2019	C	`conf`	Byte-Aware Floating-point Operations through a UNUM Computing Unit. VLSI-SoC Andrea Bocco, Tiago T. Jost, Albert Cohen, Florent de Dinechin, Yves Durand, Christian Fabre
2019	C	`conf`	Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor. ARITH Andrea Bocco, Yves Durand, Florent de Dinechin
2019	B	`conf`	Evaluating the Hardware Cost of the Posit Number System. FPL Yohann Uguen, Luc Forget, Florent de Dinechin
2019	J	`jnl`	Guest Editors Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers Javier D. Bruguera, Florent de Dinechin
2019	C	`conf`	Reflections on 10 Years of FloPoCo. ARITH Florent de Dinechin
2019	C	`conf`	Table-Based versus Shift-And-Add Constant Multipliers for FPGAs. ARITH Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Luc Forget
2019	J	`jnl`	Towards Hardware IIR Filters Computing Just Right: Direct Form I Case Study. IEEE Trans. Computers Anastasia Volkova, Matei Istoan, Florent de Dinechin, Thibault Hilaire
2018	—	`book`	Handbook of Floating-Point Arithmetic (2nd Ed.). Jean-Michel Muller, Nicolas Brunie, Florent de Dinechin, Claude-Pierre Jeannerod, Mioara Joldes, Vincent Lefèvre, Guillaume Melquiond, Nathalie Revol, Serge Torres
2018	C	`conf`	Karatsuba with Rectangular Multipliers for FPGAs. ARITH Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, Peter Zipf
2017	C	`ed.`	24th IEEE Symposium on Computer Arithmetic, ARITH 2017, London, United Kingdom, July 24-26, 2017 ARITH Neil Burgess, Javier D. Bruguera, Florent de Dinechin
2017	Misc	`conf`	A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators. FCCM Yohann Uguen, Florent de Dinechin, Steven Derrien
2017	A	`conf`	Automating the pipeline of arithmetic datapaths. DATE Matei Istoan, Florent de Dinechin
2017	B	`conf`	Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. FPL Yohann Uguen, Florent de Dinechin, Steven Derrien
2017	J	`jnl`	Hardware Division by Small Integer Constants. IEEE Trans. Computers H. Fatih Ugurdag, Florent de Dinechin, Y. Serhan Gener, Sezer Gören, Laurent-Stéphane Didier
2017	J	`jnl`	Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT. Circuits Syst. Signal Process. Hatam Abdoli, Hooman Nikmehr, Naser Movahedinia, Florent de Dinechin
2016	C	`conf`	Computing floating-point logarithms with fixed-point operations. ARITH Julien Le Maire, Nicolas Brunie, Florent de Dinechin, Jean-Michel Muller
2015	C	`conf`	Code Generators for Mathematical Functions. ARITH Nicolas Brunie, Florent de Dinechin, Olga Kupriianova, Christoph Quirin Lauter
2015	C	`conf`	Hardware Implementations of Fixed-Point Atan2. ARITH Florent de Dinechin, Matei Istoan
2014	—	`conf`	Sum-of-product architectures computing just right. ASAP Florent de Dinechin, Matei Istoan, Abdelbassat Massouri
2013	B	`conf`	Arithmetic core generation using bit heaps. FPL Nicolas Brunie, Florent de Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes, Bogdan Popa
2013	J	`jnl`	Fixed-point trigonometric functions on FPGAs. SIGARCH Comput. Archit. News Florent de Dinechin, Matei Istoan, Guillaume Sergent
2013	J	`jnl`	Floating-Point Exponentiation Units for Reconfigurable Computing. ACM Trans. Reconfigurable Technol. Syst. Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo, Bogdan Pasca
2013	J	`jnl`	On Ziv's rounding test. ACM Trans. Math. Softw. Florent de Dinechin, Christoph Quirin Lauter, Jean-Michel Muller, Serge Torres
2012	J	`jnl`	Multiplication by Rational Constants. IEEE Trans. Circuits Syst. II Express Briefs Florent de Dinechin
2012	—	`conf`	Table-Based Division by Small Integer Constants. ARC Florent de Dinechin, Laurent-Stéphane Didier
2011	—	`conf`	A mixed-precision fused multiply and add. ACSCC Nicolas Brunie, Florent de Dinechin, Benoît Dupont de Dinechin
2011	—	`conf`	An FPGA architecture for solving the Table Maker's Dilemma. ASAP Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, Alexandru Plesco
2011	J	`jnl`	Certifying the Floating-Point Implementation of an Elementary Function Using Gappa. IEEE Trans. Computers Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond
2011	J	`jnl`	Designing Custom Arithmetic Data Paths with FloPoCo. IEEE Des. Test Comput. Florent de Dinechin, Bogdan Pasca
2011	C	`conf`	The Arithmetic Operators You Will Never See in a Microprocessor. IEEE Symposium on Computer Arithmetic Florent de Dinechin
2010	—	`conf`	Automatic generation of polynomial-based hardware architectures for function evaluation. ASAP Florent de Dinechin, Mioara Joldes, Bogdan Pasca
2010	—	`conf`	Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs. FPT Álvaro Vázquez, Florent de Dinechin
2010	—	`conf`	Floating-point exponential functions for DSP-enabled FPGAs. FPT Florent de Dinechin, Bogdan Pasca
2010	—	`book`	Handbook of Floating-Point Arithmetic. Jean-Michel Muller, Nicolas Brisebarre, Florent de Dinechin, Claude-Pierre Jeannerod, Vincent Lefèvre, Guillaume Melquiond, Nathalie Revol, Damien Stehlé, Serge Torres
2010	J	`jnl`	LEMA: towards a language for reliable arithmetic. ACM Commun. Comput. Algebra Vincent Lefèvre, Philippe Théveny, Florent de Dinechin, Claude-Pierre Jeannerod, Christophe Mouilleron, David Pfannholzer, Nathalie Revol
2010	B	`conf`	Multiplicative Square Root Algorithms for FPGAs. FPL Florent de Dinechin, Mioara Joldes, Bogdan Pasca, Guillaume Revy
2010	J	`jnl`	Multipliers for floating-point double precision and beyond on FPGAs. SIGARCH Comput. Archit. News Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, Radu Tudoran
2010	B	`conf`	Pipelined FPGA Adders. FPL Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca
2009	B	`conf`	Generating high-performance custom floating-point pipelines. FPL Florent de Dinechin, Cristian Klein, Bogdan Pasca
2009	B	`conf`	Large multipliers with fewer DSP blocks. FPL Florent de Dinechin, Bogdan Pasca
2008	—	`conf`	An FPGA-specific approach to floating-point accumulation and sum-of-products. FPT Florent de Dinechin, Bogdan Pasca, Octavian Cret, Radu Tudoran
2008	J	`jnl`	Certifying floating-point implementations using Gappa CoRR Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond
2008	—	`ch.`	Digital Arithmetic. Wiley Encyclopedia of Computer Science and Engineering Florent de Dinechin, Milos D. Ercegovac, Jean-Michel Muller, Nathalie Revol
2008	—	`conf`	FPGA-Based Computation of the Inductance of Coils Used for the Magnetic Stimulation of the Nervous System. BIODEVICES (1) Ionut Trestian, Octavian Cret, Laura Cret, Lucia Vacariu, Radu Tudoran, Florent de Dinechin
2008	J	`jnl`	Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. Tech. Sci. Informatiques Jérémie Detrey, Florent de Dinechin
2008	—	`conf`	Integer and floating-point constant multipliers for FPGAs. ASAP Nicolas Brisebarre, Florent de Dinechin, Jean-Michel Muller
2008	J	`jnl`	Optimizing polynomials for floating-point implementation CoRR Florent de Dinechin, Christoph Quirin Lauter
2008	A	`conf`	When FPGAs are better at floating-point than microprocessors. FPGA Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran
2007	J	`jnl`	A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic. J. VLSI Signal Process. Jérémie Detrey, Florent de Dinechin
2007	J	`jnl`	Fast and correctly rounded logarithms in double-precision. RAIRO Theor. Informatics Appl. Florent de Dinechin, Christoph Quirin Lauter, Jean-Michel Muller
2007	B	`conf`	Floating-Point Trigonometric Functions for FPGAs. FPL Jérémie Detrey, Florent de Dinechin
2007	—	`book`	Matériel et logiciel pour l'évaluation de fonctions numériques :précision, performance et validation. Florent de Dinechin
2007	J	`jnl`	Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocess. Microsystems Jérémie Detrey, Florent de Dinechin
2007	C	`conf`	Return of the hardware floating-point elementary function. IEEE Symposium on Computer Arithmetic Jérémie Detrey, Florent de Dinechin, Xavier Pujol
2006	Misc	`conf`	Assisted verification of elementary functions using Gappa. SAC Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond
2006	C	`conf`	Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis. DSD Caroline Collange, Jérémie Detrey, Florent de Dinechin
2005	—	`conf`	A Parameterized Floating-Point Exponential Function for FPGAs. FPT Jérémie Detrey, Florent de Dinechin
2005	J	`jnl`	Multipartite Table Methods. IEEE Trans. Computers Florent de Dinechin, Arnaud Tisserand
2005	J	`jnl`	Outils pour une comparaison sans Tech. Sci. Informatiques Jérémie Detrey, Florent de Dinechin
2005	—	`conf`	Table-based polynomials for fast hardware function evaluation. ASAP Jérémie Detrey, Florent de Dinechin
2005	C	`conf`	Towards the Post-Ultimate libm. IEEE Symposium on Computer Arithmetic Florent de Dinechin, Alexey V. Ershov, Nicolas Gast
2004	B	`conf`	Second Order Function Approximation Using a Single Multiplication on FPGAs. FPL Jérémie Detrey, Florent de Dinechin
2003	B	`conf`	Software Carry-Save: A Case Study for Instruction-Level Parallelism. PaCT David Defour, Florent de Dinechin
2002	A	`conf`	Multipartite Tables in JBits for the Evaluation of Functions on FPGAs. IPDPS Jérémie Detrey, Florent de Dinechin
2001	C	`conf`	Some Improvements on Multipartite Table Methods . IEEE Symposium on Computer Arithmetic Florent de Dinechin, Arnaud Tisserand
2000	Misc	`conf`	Constant Multipliers for FPGAs. PDPTA Florent de Dinechin, Vincent Lefèvre
2000	J	`jnl`	The Price of Routing in FPGAs. J. Univers. Comput. Sci. Florent de Dinechin
1999	A	`conf`	Towards Adaptable Hierarchical Placement for FPGAs. FPGA Florent de Dinechin, Wayne Luk, Steve McKeever
1997	—	`conf`	Hierarchical Static Analysis for Improving the Complexity of Linear Algebra Algorithms. PARCO Florent de Dinechin, Tanguy Risset, Sophie Robert
1997	—	`conf`	Libraries of schedule-free operators in Alpha. ASAP Florent de Dinechin
1996	—	`conf`	A Regular VLSI Array for an Irregular Algorithm. IRREGULAR Florent de Dinechin, Doran Wilde, Sanjay V. Rajopadhye, Rumen Andonov
1996	—	`conf`	Hierarchical Static Analysis Of Structured Systems Of Affine Recurrence Equations. ASAP Florent de Dinechin, Sophie Robert