Filip Tavernier

53 papers C 1Journal 19Unranked 31

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	29.3 A 256-Channel Event-Driven Readout for Solid-State Nanopore Single-Molecule Sensing with 193pArms Noise in a 1MHz Bandwidth. ISSCC Sander Crols, Carolina Mora Lopez, Filip Tavernier, Marian Verhelst, Nick Van Helleputte
2026	J	`jnl`	A 0.5-/0.95-dB NF, 50-/25-Ω Configurable CMOS Front-End ASIC for the Readout of Liquid Argon Calorimeter in the LHC. IEEE J. Solid State Circuits Mietek Dabrowski, Filip Tavernier, Paul Leroux
2025	—	`conf`	18.8 A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR. ISSCC Bram Veraverbeke, Filip Tavernier
2025	—	`conf`	90 GHz Cryo-CMOS VCO for Enabling High Integration of Quantum Computers. NewCAS Pieter-Antonio Fernandez, Faedra Webers, Filip Tavernier, Patrick Reynaert
2025	J	`jnl`	A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology. IEEE Solid State Circuits Lett. Bram Veraverbeke, Filip Tavernier
2025	J	`jnl`	A Cryo-CMOS 800-MS/s 7-bit Charge-Injection SAR ADC With Only 4-fF Input Capacitance and 64-dB SFDR in 40-nm Bulk CMOS. IEEE J. Solid State Circuits Bram Veraverbeke, Filip Tavernier
2025	J	`jnl`	A Cryo-CMOS Triple Tail Comparator With Capacitive Over-Neutralization to Suppress Freeze-Out Induced Hysteresis. IEEE Trans. Circuits Syst. II Express Briefs Bram Veraverbeke, Filip Tavernier
2025	C	`conf`	A Digital Jitter Correction Technique For High-Speed ADC-Based Communication Links. ISCAS Tim Borremans, Jun Feng, Jonah Van Assche, Georges G. E. Gielen, Filip Tavernier
2025	—	`book`	Fully Integrated High-Voltage DC-DC and AC-DC Conversion Tuur Van Daele, Filip Tavernier
2025	J	`jnl`	Fully Integrated Optical Injection Locking With Schottky Photodiodes in 65-nm CMOS. IEEE J. Solid State Circuits Arnaud Van Mieghem, Michiel Steyaert, Filip Tavernier
2024	—	`conf`	A > 70dB Digital Readout Circuit Implemented in 65nm CMOS for 10 $\mu \mathrm{m}$ SWIR InGaAs Pixels. IEEE SENSORS Rico Jossel Maestro, Patrick Merken, Filip Tavernier
2024	J	`jnl`	Guest Editorial IEEE 2023 European Solid-State Circuits Conference. IEEE J. Solid State Circuits Filip Tavernier, Danilo Manstretta, Ronan A. R. van der Zee
2024	J	`jnl`	Monolithic 230-V IEEE J. Solid State Circuits Tuur Van Daele, Filip Tavernier
2023	—	`conf`	A 10 GHz Quadruple-Tail Comparator with Double Feedforward Paths and Minimal Delay Slope in 28 nm CMOS. ESSCIRC Zongyuan Li, Filip Tavernier
2023	—	`conf`	A Fully Integrated 230 VRMS-to-12 VDC AC-DC Converter Achieving 9 mW/mm VLSI Technology and Circuits Tuur Van Daele, Filip Tavernier
2023	J	`jnl`	Fully Integrating a 400 V-to-12 V DC-DC Converter in High-Voltage CMOS. IEEE J. Solid State Circuits Tuur Van Daele, Filip Tavernier
2023	—	`book`	Multi-Gigahertz Nyquist Analog-to-Digital Converters - Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies, 3 Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier
2022	—	`conf`	A 240V to 47.5 V Fully Integrated Switched-Capacitor Converter in GaN Achieving 62.6% Efficiency at 220 mW/mm PRIME Bram Veraverbeke, Tim Thielemans, Tuur Van Daele, Filip Tavernier
2022	J	`jnl`	A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity. IEEE Trans. Circuits Syst. I Regul. Pap. Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier
2022	—	`conf`	A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET. VLSI Technology and Circuits Athanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier
2022	—	`conf`	A 400-to-12 V Fully Integrated Switched-Capacitor DC-DC Converter Achieving 119 mW/mm2 at 63.6 % Efficiency. CICC Tuur Van Daele, Filip Tavernier
2022	—	`conf`	Photoplethysmography (PPG) Sensor Circuit Design Techniques. CICC Qiuyang Lin, Christina Avidikou, Filip Tavernier, Nick Van Helleputte
2021	J	`jnl`	A 134 DB Dynamic Range Noise Shaping Slope Light-to-Digital Converter for Wearable Chest PPG Applications. IEEE Trans. Biomed. Circuits Syst. Qiuyang Lin, Shuang Song, Roland Van Wegberg, Wim Sijbers, Dwaipayan Biswas, Mario Konijnenburg, Chris Van Hoof, Filip Tavernier, Nick Van Helleputte
2021	—	`conf`	A 28μW 134dB DR 2nd-Order Noise-Shaping Slope Light-to-Digital Converter for Chest PPG Monitoring. ISSCC Qiuyang Lin, Shuang Song, Roland Van Wegberg, Mario Konijnenburg, Dwaipayan Biswas, Chris Van Hoof, Filip Tavernier, Nick Van Helleputte
2020	J	`jnl`	1310/1550 nm Optical Receivers With Schottky Photodiode in Bulk CMOS. IEEE J. Solid State Circuits Wouter Diels, Michiel Steyaert, Filip Tavernier
2020	—	`conf`	A 1 GS/s Reconfigurable BW 2 VLSI Circuits Yifan Lyu, Filip Tavernier
2020	J	`jnl`	A 119dB Dynamic Range Charge Counting Light-to-Digital Converter For Wearable PPG/NIRS Monitoring Applications. IEEE Trans. Biomed. Circuits Syst. Qiuyang Lin, Jiawei Xu, Shuang Song, Arjan Breeschoten, Mario Konijnenburg, Chris Van Hoof, Filip Tavernier, Nick Van Helleputte
2020	J	`jnl`	A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs. IEEE J. Solid State Circuits Yifan Lyu, Filip Tavernier
2020	—	`conf`	A 4V-0.55V Input Fully Integrated Switched-Capacitor Converter Enabling Dynamic Voltage Domain Stacking and Achieving 80.1% Average Efficiency. VLSI Circuits Tim Thielemans, Filip Tavernier
2020	J	`jnl`	A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS. IEEE J. Solid State Circuits Athanasios T. Ramkaj, Juan Carlos Pena Ramos, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Marian Verhelst, Filip Tavernier
2019	—	`conf`	A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS. ESSCIRC Athanasios T. Ramkaj, Michiel S. J. Steyaert, Filip Tavernier
2019	—	`conf`	A 196μW, Reconfigurable Light-to-Digital Converter with 119dB Dynamic Range, for Wearable PPG/NIRS Sensors. VLSI Circuits Qiuyang Lin, Jiawei Xu, Shuang Song, Arjan Breeschoten, Mario Konijnenburg, Mingyi Chen, Chris Van Hoof, Filip Tavernier, Nick Van Helleputte
2019	—	`conf`	A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs. ESSCIRC Yifan Lyu, Filip Tavernier
2019	—	`conf`	A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS. ISSCC Athanasios Ramkaj, Juan Carlos Pena Ramos, Yifan Lyu, Maarten Strackx, Marcel J. M. Pelgrom, Michiel Steyaert, Marian Verhelst, Filip Tavernier
2019	—	`conf`	A Fully-Integrated 6: 1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm PRIME Tuur Van Daele, Elly De Pelecijn, Tim Thielemans, Michiel Steyaert, Filip Tavernier
2019	J	`jnl`	A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Filipe D. Baumgratz, Carlos E. Saavedra, Michiel Steyaert, Filip Tavernier, Sergio Bampi
2019	—	`conf`	Optical Receiver with Schottky Photodiode and TIA with High Gain Amplifier in 28nm Bulk CMOS. ESSCIRC Wouter Diels, Michiel Steyaert, Filip Tavernier
2018	J	`jnl`	40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor. IEEE Trans. Circuits Syst. I Regul. Pap. Filipe D. Baumgratz, Sandro Binsfeld Ferreira, Michiel S. J. Steyaert, Sergio Bampi, Filip Tavernier
2018	J	`jnl`	A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS. IEEE J. Solid State Circuits Athanasios Ramkaj, Maarten Strackx, Michiel S. J. Steyaert, Filip Tavernier
2018	—	`conf`	A 1310/1550 nm Fully-Integrated Optical Receiver with Schottky Photodiode and Low-Noise Transimpedance Amplifier in 40 nm Bulk CMOS. ESSCIRC Wouter Diels, Michiel Steyaert, Filip Tavernier
2018	—	`conf`	A 400GΩ Input-Impedance, 220MVpp Linear-Input-Range, 2.8Vpp CM-Interference-Tolerant Active Electrode for Non-Contact Capacitively Coupled ECG Acquisition. VLSI Circuits Mingyi Chen, Ivan Dario Castro, Qiuyang Lin, Tom Torfs, Filip Tavernier, Chris Van Hoof, Nick Van Helleputte
2018	—	`conf`	A Charge-Sharing Bandpass Filter Topology with Boosted Q-Factor in 40-NM CMOS. SBCCI Filipe D. Baumgratz, Sandro B. Ferreira, Michiel Steyaert, Sergio Bampi, Filip Tavernier
2018	—	`conf`	A capacitive DC-DC converter for stacked loads with wide range DVS achieving 98.2% peak efficiency in 40nm CMOS. CICC Tim Thielemans, Nicolas Butzen, Athanasios Sarafianos, Michiel Steyaert, Filip Tavernier
2017	—	`conf`	A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS. ESSCIRC Athanasios Ramkaj, Maarten Strackx, Michiel Steyaert, Filip Tavernier
2017	—	`conf`	Modelling, design and characterization of Schottky diodes in 28nm bulk CMOS for 850/1310/1550nm fully integrated optical receivers. ESSDERC Wouter Diels, Michiel Steyaert, Filip Tavernier
2017	—	`conf`	Schottky diodes in 40nm bulk CMOS for 1310nm high-speed optical receivers. OFC Wouter Diels, Michiel Steyaert, Filip Tavernier
2016	J	`jnl`	10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Tao Zhang, Ping Gui, Sudipto Chakraborty, Tianwei Liu, Guoying Wu, Paulo Moreira, Filip Tavernier
2015	—	`conf`	When hardware is free, power is expensive! Is integrated power management the solution? ESSCIRC Michiel Steyaert, Filip Tavernier, Hans Meyvaert, Athanasios Sarafianos, Nicolas Butzen
2010	—	`conf`	A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode. ESSCIRC Filip Tavernier, Michiel Steyaert
2009	—	`conf`	A low power, area efficient limiting amplifier in 90nm CMOS. ESSCIRC Filip Tavernier, Michiel Steyaert
2009	J	`jnl`	High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS. IEEE J. Solid State Circuits Filip Tavernier, Michel S. J. Steyaert
2008	—	`conf`	A high-speed fully integrated optical receiver in standard 130nm CMOS. ICECS Filip Tavernier, Michiel Steyaert
2008	—	`conf`	Power efficient 4.5Gbit/s optical receiver in 130nm CMOS with integrated photodiode. ESSCIRC Filip Tavernier, Michiel Steyaert