Fengbin Tu - RankMe

76 papers A* 17A 6C 3Journal 35Unranked 15

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding. ISSCC Pingcheng Dong, Yonghao Tan, Xuejiao Liu, Peng Luo, Yu Liu, Di Pang, Songchen Ma, Xijie Huang, Shih-Yang Liu, Dong Zhang, Zhichao Lu, Luhong Liang, Chi-Ying Tsui, Fengbin Tu, Liang Zhao, Kwang-Ting Cheng
2026	J	`jnl`	ETCIM: Error-Tolerant Digital CIM Processor With Redundancy-Free Hard Error Repair and Run-Time Soft Error Correction. IEEE J. Solid State Circuits Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2026	A*	`conf`	HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture With Unified Low-Cost Iterative Error Correction. HPCA Zhen He, Yiqi Wang, Zhiheng Yue, Zihan Wu, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2026	J	`jnl`	MRCIM: A Many-Core Reconfigurable Computing-in-Memory Processor Combining CPU and Tensor Modes for NN Acceleration. IEEE Trans. Circuits Syst. I Regul. Pap. Zhen He, Yiqi Wang, Zihan Wu, Huiming Han, Shaojun Wei, Yang Hu, Chao Li, Fengbin Tu, Shouyi Yin
2026	A*	`conf`	VAR-Turbo: Unlocking the Potential of Visual Autoregressive Models Through Dual Redundancy. HPCA Xujiang Xiang, Fengbin Tu
2025	—	`conf`	A 28nm 0.22μJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation. ISSCC Pingcheng Dong, Yonghao Tan, Xuejiao Liu, Peng Luo, Yu Liu, Luhong Liang, Yitong Zhou, Di Pang, Manto Yung, Dong Zhang, Xijie Huang, Shih-Yang Liu, Yongkun Wu, Fengshi Tian, Chi-Ying Tsui, Fengbin Tu, Kwang-Ting Cheng
2025	J	`jnl`	CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction. IEEE J. Solid State Circuits Zhiheng Yue, Yang Wang, Huizheng Wang, Ruiqi Guo, Fengbin Tu, Jianxun Yang, Shaojun Wei, Yang Hu, Shouyi Yin
2025	A	`conf`	CoXplorer: Multi-Staged Co-Exploration Framework for AI Model Compression and Accelerator Design. ICCAD Songchen Ma, Junyi Wu, Yonghao Tan, Pingcheng Dong, Peng Luo, Di Pang, Yu Liu, Xuejiao Liu, Luhong Liang, Kwang-Ting Cheng, Fengbin Tu
2025	J	`jnl`	CompAir: Synergizing Complementary PIMs and In-Transit NoC Computation for Efficient LLM Acceleration. CoRR Hongyi Li, Songchen Ma, Huanyu Qu, Weihao Zhang, Jia Chen, Junfeng Lin, Fengbin Tu, Rong Zhao
2025	A*	`conf`	ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction. HPCA Zhen He, Yiqi Wang, Zihan Wu, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2025	J	`jnl`	Exploiting the Memory-Compute-Coupling Feature for CIM Accelerator Design Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yongkun Wu, Xiaomeng Wang, Jia Chen, Zhenhua Zhu, Jingyu He, Pingcheng Dong, Yonghao Tan, Xin Zhao, Liang Chang, Yu Wang, Fengbin Tu, Chi-Ying Tsui, Kwang-Ting Cheng
2025	—	`conf`	PAMA: Large-Scale GNN Acceleration with Pre-Aggregation in Multi-Node Architecture. ASAP Weiwei Wu, Fengbin Tu, Shaojun Wei, Xiangyu Li, Yang Hu, Shouyi Yin
2025	J	`jnl`	Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design. IEEE Trans. Computers Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
2025	A	`conf`	SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis. DATE Kunming Shao, Fengshi Tian, Xiaomeng Wang, Jiakun Zheng, Jia Chen, Jingyu He, Hui Wu, Jinbo Chen, Xihao Guan, Yi Deng, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui
2025	J	`jnl`	TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration. IEEE J. Solid State Circuits Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Fengbin Tu, Shouyi Yin
2024	—	`conf`	15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch. ISSCC Zhiheng Yue, Xujiang Xiang, Fengbin Tu, Yang Wang, Yiming Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models. ISSCC Ruiqi Guo, Lei Wang, Xiaofeng Chen, Hao Sun, Zhiheng Yue, Yubin Qin, Huiming Han, Yang Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm VLSI Technology and Circuits Ruiqi Guo, Xiaofeng Chen, Lei Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A	`conf`	AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator Using Adaptive Posit. DATE Jingyu He, Fengbin Tu, Kwang-Ting Cheng, Chi-Ying Tsui
2024	J	`jnl`	DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiajun Zhou, Jiajun Wu, Yizhao Gao, Yuhao Ding, Chaofan Tao, Boyu Li, Fengbin Tu, Kwang-Ting Cheng, Hayden Kwok-Hay So, Ngai Wong
2024	—	`conf`	ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction. VLSI Technology and Circuits Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2024	A*	`conf`	Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture. ISCA Zhiheng Yue, Huizheng Wang, Jiahao Fang, Jinyi Deng, Guangyang Lu, Fengbin Tu, Ruiqi Guo, Yuxuan Li, Yubin Qin, Yang Wang, Chao Li, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2024	J	`jnl`	HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. Xin Zhao, Liang Chang, Dongqi Fan, Zhicheng Hu, Ting Yue, Fengbin Tu, Jun Zhou
2024	J	`jnl`	MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity. IEEE J. Solid State Circuits Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin
2024	A*	`conf`	Multi-Issue Butterfly Architecture for Sparse Convex Quadratic Programming. MICRO Maolin Wang, Ian McInerney, Bartolomeo Stellato, Fengbin Tu, Stephen P. Boyd, Hayden Kwok-Hay So, Kwang-Ting Cheng
2024	J	`jnl`	SWG: an architecture for sparse weight gradient computation. Sci. China Inf. Sci. Weiwei Wu, Fengbin Tu, Xiangyu Li, Shaojun Wei, Shouyi Yin
2024	J	`jnl`	SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis. CoRR Kunming Shao, Fengshi Tian, Xiaomeng Wang, Jiakun Zheng, Jia Chen, Jingyu He, Hui Wu, Jinbo Chen, Xihao Guan, Yi Deng, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui
2023	J	`jnl`	A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications. CoRR Xiaomeng Wang, Fengshi Tian, Xizi Chen, Jiakun Zheng, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting Cheng, Chi-Ying Tsui
2023	A*	`conf`	AutoDCIM: An Automated Digital CIM Compiler. DAC Jia Chen, Fengbin Tu, Kunming Shao, Fengshi Tian, Xiao Huo, Chi-Ying Tsui, Kwang-Ting Cheng
2023	—	`conf`	BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare. ESSCIRC Fengshi Tian, Xiaomeng Wang, Jinbo Chen, Jiakun Zheng, Hui Wu, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting (Tim) Cheng
2023	J	`jnl`	DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference. CoRR Jiajun Zhou, Jiajun Wu, Yizhao Gao, Yuhao Ding, Chaofan Tao, Boyu Li, Fengbin Tu, Kwang-Ting Cheng, Hayden Kwok-Hay So, Ngai Wong
2023	A*	`conf`	ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification. ISCA Siqi Li, Fengbin Tu, Liu Liu, Jilan Lin, Zheng Wang, Yangwook Kang, Yufei Ding, Yuan Xie
2023	—	`conf`	MuITCIM: A 28nm $2.24 \mu\mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. ISSCC Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin
2023	A*	`conf`	PIM-HLS: An Automatic Hardware Generation Tool for Heterogeneous Processing-In-Memory-based Neural Network Accelerators. DAC Yu Zhu, Zhenhua Zhu, Guohao Dai, Fengbin Tu, Hanbo Sun, Kwang-Ting Cheng, Huazhong Yang, Yu Wang
2023	J	`jnl`	ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. IEEE J. Solid State Circuits Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2023	J	`jnl`	Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips. IEEE Trans. Circuits Syst. I Regul. Pap. Shaojun Wei, Xinhan Lin, Fengbin Tu, Yang Wang, Leibo Liu, Shouyi Yin
2023	J	`jnl`	SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fengbin Tu, Yiqi Wang, Ling Liang, Yufei Ding, Leibo Liu, Shaojun Wei, Shouyi Yin, Yuan Xie
2023	J	`jnl`	SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization. IEEE Trans. Circuits Syst. I Regul. Pap. Yiqi Wang, Fengbin Tu, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2023	J	`jnl`	SPG: Structure-Private Graph Database via SqueezePIR. Proc. VLDB Endow. Ling Liang, Jilan Lin, Zheng Qu, Ishtiyaque Ahmad, Fengbin Tu, Trinabh Gupta, Yufei Ding, Yuan Xie
2023	J	`jnl`	STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. Weiwei Wu, Fengbin Tu, Mengqi Niu, Zhiheng Yue, Leibo Liu, Shaojun Wei, Xiangyu Li, Yang Hu, Shouyi Yin
2023	—	`conf`	TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. ISSCC Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin
2023	A*	`conf`	Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. MICRO Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Boxiao Han, Hongjun He, Fengbin Tu, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	J	`jnl`	Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. CoRR Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Fengbin Tu, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	J	`jnl`	TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. IEEE J. Solid State Circuits Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2022	—	`conf`	A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. ISSCC Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2022	—	`conf`	A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. ISSCC Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2022	A	`conf`	Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU. DATE Ling Liang, Zhaodong Chen, Lei Deng, Fengbin Tu, Guoqi Li, Yuan Xie
2022	J	`jnl`	Alleviating Datapath Conflicts and Design Centralization in Graph Analytics Acceleration. CoRR Haiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan, Yuan Xie
2022	A*	`conf`	Alleviating datapath conflicts and design centralization in graph analytics acceleration. DAC Haiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan, Yuan Xie
2022	A*	`conf`	DOTA: detect and omit weak attentions for scalable transformer acceleration. ASPLOS Zheng Qu, Liu Liu, Fengbin Tu, Zhaodong Chen, Yufei Ding, Yuan Xie
2022	J	`jnl`	Dynamic Sparse Attention for Scalable Transformer Acceleration. IEEE Trans. Computers Liu Liu, Zheng Qu, Zhaodong Chen, Fengbin Tu, Yufei Ding, Yuan Xie
2022	J	`jnl`	GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating. IEEE Trans. Circuits Syst. I Regul. Pap. Jianxun Yang, Fengbin Tu, Yixuan Li, Yiqi Wang, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	J	`jnl`	H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ling Liang, Zheng Qu, Zhaodong Chen, Fengbin Tu, Yujie Wu, Lei Deng, Guoqi Li, Peng Li, Yuan Xie
2022	A*	`conf`	INSPIRE: in-storage private information retrieval via protocol and architecture co-design. ISCA Jilan Lin, Ling Liang, Zheng Qu, Ishtiyaque Ahmad, Liu Liu, Fengbin Tu, Trinabh Gupta, Yufei Ding, Yuan Xie
2021	A*	`conf`	ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training. DAC Xinhan Lin, Liang Sun, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei, Shouyi Yin
2021	A	`conf`	Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper. ICCAD Hussam Amrouch, Jian-Jia Chen, Kaushik Roy, Yuan Xie, Indranil Chakraborty, Wenqin Huangfu, Ling Liang, Fengbin Tu, Cheng Wang, Mikail Yayla
2021	J	`jnl`	Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning". IEEE J. Solid State Circuits Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2021	J	`jnl`	Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning. IEEE J. Solid State Circuits Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2021	J	`jnl`	H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks. CoRR Ling Liang, Zheng Qu, Zhaodong Chen, Fengbin Tu, Yujie Wu, Lei Deng, Guoqi Li, Peng Li, Yuan Xie
2020	A*	`conf`	DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture. MICRO Liu Liu, Zheng Qu, Lei Deng, Fengbin Tu, Shuangchen Li, Xing Hu, Zhenyu Gu, Yufei Ding, Yuan Xie
2020	A*	`conf`	STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction. DAC Feng Xiong, Fengbin Tu, Man Shi, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin
2019	J	`jnl`	A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Shaojun Wei
2019	—	`conf`	MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions. NEWCAS Weiwei Wu, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei
2019	J	`jnl`	Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. IEEE Trans. Parallel Distributed Syst. Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Jishen Zhao, Cong Xu, Shuangchen Li, Yuan Xie, Shaojun Wei
2019	J	`jnl`	Reconfigurable Architecture for Neural Approximation in Multimedia Computing. IEEE Trans. Circuits Syst. Video Technol. Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2019	—	`conf`	Towards Efficient Compact Network Training on Edge-Devices. ISVLSI Feng Xiong, Fengbin Tu, Shouyi Yin, Shaojun Wei
2018	J	`jnl`	A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications. IEEE J. Solid State Circuits Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Shixuan Zheng, Tianyi Lu, Jiangyuan Gu, Leibo Liu, Shaojun Wei
2018	C	`conf`	An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing. ISCAS Zhihui Wang, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei
2018	C	`conf`	Bit-width Adaptive Accelerator Design for Convolution Neural Network. ISCAS Jianxin Guo, Shouyi Yin, Peng Ouyang, Fengbin Tu, Shibin Tang, Leibo Liu, Shaojun Wei
2018	J	`jnl`	GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiale Yan, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei
2018	A*	`conf`	LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA. DAC Xinhan Lin, Shouyi Yin, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei
2018	A*	`conf`	RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM. ISCA Fengbin Tu, Weiwei Wu, Shouyi Yin, Leibo Liu, Shaojun Wei
2017	—	`conf`	AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs. NVMSA Shibin Tang, Shouyi Yin, Shixuan Zheng, Peng Ouyang, Fengbin Tu, Leiyue Yao, Jinzhou Wu, Wenming Cheng, Leibo Liu, Shaojun Wei
2017	J	`jnl`	Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. IEEE Trans. Very Large Scale Integr. Syst. Fengbin Tu, Shouyi Yin, Peng Ouyang, Shibin Tang, Leibo Liu, Shaojun Wei
2015	C	`conf`	Neural approximating architecture targeting multiple application domains. ISCAS Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2015	A	`conf`	RNA: a reconfigurable architecture for hardware neural acceleration. DATE Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei