Feng Zhang - RankMe

56 papers A* 1C 7Journal 27Unranked 20

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 28-nm 88.3-TFLOPS/W POSIT-Approximate-Calculation-Based Digital Computing-in-Memory Macro Incorporating Final-Cycle Fusion and Joint Skipping. IEEE J. Solid State Circuits Hao Wu, Yong Chen, Ming Li, Bingxin Zhang, Rui Zhang, Yiyang Yuan, Yiming Yang, Jinshan Yue, Xinghua Wang, Xiaoran Li, Feng Zhang
2025	—	`conf`	14.5 A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference. ISSCC Yiyang Yuan, Bingxin Zhang, Yiming Yang, Yishan Luo, Qirui Chen, Shidong Lv, Hao Wu, Cailian Ma, Ming Li, Jinshan Yue, Xinghua Wang, Guozhong Xing, Pui-In Mak, Xiaoran Li, Feng Zhang
2025	J	`jnl`	A 28 nm 75.6 KOPS 13 nJ Computing-in-Memory Pipeline Number Theoretic Transform Accelerator for PQC. IEEE Trans. Circuits Syst. II Express Briefs Jialiang Zhu, Yiyang Yuan, Long Nie, Weiye Tang, Ming Li, Hao Wu, Xiaojin Zhao, Guozhong Xing, Feng Zhang
2025	J	`jnl`	A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity. IEEE J. Solid State Circuits Hao Wu, Yong Chen, Yiyang Yuan, Jinshan Yue, Xinghua Wang, Xiaoran Li, Feng Zhang
2025	J	`jnl`	A General-Purpose Computing Core With Cooperative Motion Detection and Feature Extraction for Always-On PWM Image Sensors. IEEE Trans. Very Large Scale Integr. Syst. Jinyu Gao, Ye Zhao, Ziyuan Wang, Long Chen, Aoming Zhan, Qihang Jiang, Feng Zhang, Yong Chen, Shushan Qiao
2025	J	`jnl`	A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications. IEEE Trans. Very Large Scale Integr. Syst. Jun Wang, Shengzhe Yan, Xiangqu Fu, Zhihang Qian, Zhi Li, Zeyu Guo, Zhuoyu Dai, Zhaori Cong, Chunmeng Dou, Feng Zhang, Jinshan Yue, Dashan Shang
2025	J	`jnl`	An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet. IEEE Trans. Very Large Scale Integr. Syst. Zhihang Qian, Shengzhe Yan, Zhuoyu Dai, Zeyu Guo, Zhaori Cong, Yifan He, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu
2025	A*	`conf`	Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory. DAC Yi Li, Zijian Ye, Xiangqu Fu, Songqi Wang, Shucheng Du, Ning Lin, Dashan Shang, Jinshan Yue, Zhongrui Wang, Xiaojuan Qi, Feng Zhang, Han Wang
2025	J	`jnl`	SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer. IEEE Trans. Circuits Syst. I Regul. Pap. Xiangqu Fu, Jinshan Yue, Muhammad Faizan, Zhi Li, Qiang Huo, Feng Zhang
2024	—	`conf`	34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC. ISSCC Yiyang Yuan, Yiming Yang, Xinghua Wang, Xiaoran Li, Cailian Ma, Qirui Chen, Meini Tang, Xi Wei, Zhixian Hou, Jialiang Zhu, Hao Wu, Qirui Ren, Guozhong Xing, Pui-In Mak, Feng Zhang
2024	J	`jnl`	A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. IEEE Trans. Circuits Syst. I Regul. Pap. Hao Wu, Yong Chen, Yiyang Yuan, Jinshan Yue, Xiangqu Fu, Qirui Ren, Qing Luo, Pui-In Mak, Xinghua Wang, Feng Zhang
2024	J	`jnl`	A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture. IEEE J. Solid State Circuits Shengzhe Yan, Jinshan Yue, Chaojie He, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou, Wenyu Sun, Xueqing Li, Chunmeng Dou, Feng Zhang, Huazhong Yang, Yongpan Liu, Ming Liu
2024	—	`conf`	A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications. VLSI Technology and Circuits Zhuoyu Dai, Shengzhe Yan, Zhaori Cong, Zeyu Guo, Yifan He, Wenyu Sun, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu, Ming Liu
2024	J	`jnl`	A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhuoyu Dai, Feibin Xiang, Xiangqu Fu, Yifan He, Wenyu Sun, Yongpan Liu, Guanhua Yang, Feng Zhang, Jinshan Yue, Ling Li
2023	J	`jnl`	A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference. IEEE J. Solid State Circuits Wang Ye, Linfang Wang, Zhidao Zhou, Junjie An, Weizeng Li, Hanghang Gao, Zhi Li, Jinshan Yue, Hongyang Hu, Xiaoxin Xu, Jianguo Yang, Jing Liu, Dashan Shang, Feng Zhang, Jinghui Tian, Chunmeng Dou, Qi Liu, Ming Liu
2023	—	`conf`	A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. ISSCC Jinshan Yue, Chaojie He, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou, Wenyu Sun, Xueqing Li, Chunmeng Dou, Feng Zhang, Huazhong Yang, Yongpan Liu, Ming Liu
2023	J	`jnl`	A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF. IEEE Trans. Very Large Scale Integr. Syst. Qirui Ren, Qiang Huo, Zhisheng Chen, Qi Gao, Yiming Wang, Yiming Yang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei, Xinghua Wang, Feng Zhang, Yong Chen, Pui-In Mak
2023	J	`jnl`	P IEEE Trans. Circuits Syst. I Regul. Pap. Xiangqu Fu, Qirui Ren, Hao Wu, Feibin Xiang, Qing Luo, Jinshan Yue, Yong Chen, Feng Zhang
2022	J	`jnl`	A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection. Sensors Qirui Ren, Chengying Chen, Danian Dong, Xiaoxin Xu, Yong Chen, Feng Zhang
2022	J	`jnl`	Fast and Reconfigurable Logic Synthesis in Memristor Crossbar Array. Adv. Intell. Syst. Wei Wang, Sen Liu, Qingjiang Li, Tuo Shi, Feng Zhang, Haijun Liu, Nan Li, Yongzhou Wang, Yi Sun, Bing Song, Hui Xu, Qi Liu
2021	—	`conf`	24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m ISSCC Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Qiao Wang, Haijun Jiang, Jie Yu, Danian Dong, Feng Zhang, Hangbing Lv, Ming Liu
2021	J	`jnl`	Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control. IEEE Trans. Circuits Syst. II Express Briefs Linfang Wang, Wang Ye, Chunmeng Dou, Xin Si, Xiaoxin Xu, Jing Liu, Dashan Shang, Jianfeng Gao, Feng Zhang, Yongpan Liu, Meng-Fan Chang, Qi Liu
2021	J	`jnl`	Investigation of weight updating modes on oxide-based resistive switching memory synapse towards neuromorphic computing applications. Sci. China Inf. Sci. Qingting Ding, Tiancheng Gong, Jie Yu, Xiaoxin Xu, Xiaoyan Li, Hangbing Lv, Jianguo Yang, Qing Luo, Peng Yuan, Feng Zhang, Ming Liu
2020	J	`jnl`	A 108 F IEEE Trans. Circuits Syst. Qiang Zhao, Wenhan Zheng, Xiaojin Zhao, Yuan Cao, Feng Zhang, Man-Kay Law
2020	—	`conf`	A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm VLSI Circuits Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Hangbing Lv, Feng Zhang, Xiaoyang Zeng, Meng-Fan Chang, Ming Liu
2020	J	`jnl`	A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications. IEEE Trans. Circuits Syst. II Express Briefs Fei Tan, Yiming Wang, Yiming Yang, Liran Li, Tian Wang, Feng Zhang, Xinghua Wang, Jianfeng Gao, Yongpan Liu
2019	J	`jnl`	A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs Yiming Wang, Yun Li, Haihua Shen, Dongyu Fan, Wei Wang, Ling Li, Qi Liu, Feng Zhang, Xinghua Wang, Meng-Fan Chang, Ming Liu
2019	—	`conf`	A Fluctuation Model of a Hf02 RRAM Cell for Memory Circuit Designs. SMACD Feng Zhang, Linan Li, Qiang Huo, Cong Fang, Wenqiang Ba
2019	—	`conf`	A Modeling Approach for 7nm Technology Node Area-Consuming Circuit Optimization and Beyond. SMACD Qiang Huo, Zhenhua Wu, Feng Zhang, Ling Li
2019	J	`jnl`	A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond. CoRR Qiang Huo, Zhenhua Wu, Weixing Huang, Xingsheng Wang, Geyu Tang, Jiaxin Yao, Yongpan Liu, Feng Zhang, Ling Li, Ming Liu
2019	C	`conf`	Adaptive Power Optimization for Mobile Traffic Based on Machine Learning. CSCWD Wei Zhao, Haihua Shen, Feng Zhang, Huazhe Tan
2019	J	`jnl`	HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection. CoRR Renjie Lu, Haihua Shen, Feng Zhang, Huawei Li, Wei Zhao, Xiaowei Li
2019	—	`ed.`	Machine Learning and Medical Engineering for Cardiovascular Health and Intravascular Imaging and Computer Assisted Stenting - First International Workshop, MLMECH 2019, and 8th Joint International Workshop, CVII-STENT 2019, Held in Conjunction with MICCAI 2019, Shenzhen, China, October 13, 2019, Proceedings MLMECH/CVII-STENT@MICCAI Hongen Liao, Simone Balocco, Guijin Wang, Feng Zhang, Yongpan Liu, Zijian Ding, Luc Duong, Renzo Phellan, Guillaume Zahnd, Katharina Breininger, Shadi Albarqouni, Stefano Moriconi, Su-Lin Lee, Stefanie Demirci
2019	—	`conf`	Particle Swarm Optimization for Great Enhancement in Semi-supervised Retinal Vessel Segmentation with Generative Adversarial Networks. MLMECH/CVII-STENT@MICCAI Qiang Huo, Geyu Tang, Feng Zhang
2018	J	`jnl`	A 0.6V, 8.4uW AFE circuit for biomedical signal recording. Microelectron. J. Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang
2018	C	`conf`	A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application. ISCAS Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang
2018	J	`jnl`	LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection. IEEE Trans. Very Large Scale Integr. Syst. Haihua Shen, Huazhe Tan, Huawei Li, Feng Zhang, Xiaowei Li
2018	—	`conf`	The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory. VLSI-DAT Feng Zhang, Dongyu Fan, Qi-Peng Lin, Qiang Huo, Yun Li, Lan Dai, Cheng-Ying Chen, Haihua Shen
2017	—	`conf`	A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement. CICC Xiaowei Han, Qian Jia, Hongbin Sun, Longfei Wang, Huaqiang Wu, Yimao Cai, Feng Zhang, Yongyi Xie, Fangxu Dong, Xiaoguang Wang, Xiaofei Xue, Li Pang, Xiaoqing Zhao, Mengnan Wu, Pu Bai, Qi Liu, Hangbing Lv, Bing Yu, Chao Zhao, He Qian, Ru Huang, Ming Liu, Yumei Zhou, Nanning Zheng, Qiwei Ren
2017	—	`conf`	A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range. A-SSCC Feng Zhang, Dongyu Fan, Yuan Duan, Jin Li, Cong Fang, Yun Li, Xiaowei Han, Lan Dai, Cheng-Ying Chen, Jinshun Bi, Ming Liu, Meng-Fan Chang
2017	—	`conf`	A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. A-SSCC Nan Qi, Yuhang Kang, Qipeng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma, Zuyuan He, Ming Liu, Feng Zhang, Patrick Yin Chiang
2017	—	`conf`	A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection. ASICON Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang
2017	—	`conf`	An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects. ASICON Yun Li, Haihua Shen, Ce Li, Feng Zhang
2017	J	`jnl`	Wide-range tracking technique for process-variation-robust clock and data recovery applications. Frontiers Inf. Technol. Electron. Eng. Junsheng Lv, You Li, Yumei Zhou, Jianzhong Zhao, Haihua Shen, Feng Zhang
2016	J	`jnl`	A 128 Kb HfO IEICE Electron. Express Cheng-Ying Chen, Hongbin Sun, Haihua Shen, Feng Zhang
2016	C	`conf`	A 1V, 1.1mW mixed-signal hearing aid SoC in 0.13μm CMOS process. ISCAS Chengying Chen, Liming Chen, Jun Fan, Zenghui Yu, Jun Yang, Xiaoyu Hu, Yong Hei, Feng Zhang
2015	—	`conf`	A PVT variation tolerant and low power 5Gb/s clock and data recovery circuit for PCI-E 2.0/USB 3.0. ASICON Feng Zhang, Hao Ju, Chengying Chen
2013	—	`conf`	A novel equalizer for the high-loss backplane at Nyquist frequency. ASICON You Li, Feng Zhang, Yumei Zhou
2012	C	`conf`	A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line. ISCAS Shuai Chen, Hao Li, Kai Jia, Yue Wang, Xiaobing Shi, Feng Zhang
2012	—	`conf`	An efficient physical coding sublayer for PCI express in 65nm CMOS. ISPACS Qihao Liu, Huihui Weng, Feng Zhang, Jianzhong Zhao, Junsheng Lv, You Li
2011	C	`conf`	A novel SST transmitter with mutually decoupled impedance self-calibration and equalization. ISCAS Shuai Chen, Liqiong Yang, Hua Jing, Feng Zhang, Zhuo Gao
2011	J	`jnl`	Sinusoidal Clock Sampling for Multigigahertz ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Rui Bai, Jingguang Wang, Lingli Xia, Feng Zhang, Zongren Yang, Weiwu Hu, Patrick Chiang
2009	C	`conf`	A 10Gb/s Wire-line Transceiver with Half Rate Period Calibration CDR. ISCAS Zhuo Gao, Hang Yu, Patrick Chiang, Yi Yang, Feng Zhang
2008	—	`conf`	A High Speed CMOS Transmitter and Rail-to-Rail Receiver. DELTA Feng Zhang, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu
2007	C	`conf`	DRM - the Digital Radio on the Way. ISCC Shuzheng Xu, Pengjun Wang, Feng Zhang, Huazhong Yang
2006	—	`conf`	A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection. APCCAS Yongpan Liu, Yu Wang, Feng Zhang, Rong Luo, Hui Wang