Felipe S. Marranghello

26 papers A* 2C 7Journal 6Unranked 11

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations. IEEE J. Emerg. Sel. Topics Circuits Syst. Cesar de S. Dias, Felipe S. Marranghello, Raphael Martins Brum, Paulo F. Butzen
2021	A*	`conf`	LUT-Based Optimization For ASIC Design Flow. DAC Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2020	J	`jnl`	Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas
2020	A*	`conf`	SAT-Sweeping Enhanced for Logic Synthesis. DAC Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2020	J	`jnl`	maj-n Logic Synthesis for Emerging Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Augusto Neutzling, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas
2019	J	`jnl`	Four-Level Forms for Memristive Material Implication Logic. IEEE Trans. Very Large Scale Integr. Syst. Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2019	—	`conf`	Threshold Physical Unclonable Functions. ISMVL Felipe S. Marranghello, Yang Yu, Elena Dubrova
2018	—	`conf`	Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. SBCCI Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas
2018	—	`conf`	One-Sided Countermeasures for Side-Channel Attacks Can Backfire. WISEC Yang Yu, Felipe S. Marranghello, Victor Diges Teijeira, Elena Dubrova
2017	—	`conf`	Binary adder circuit design using emerging MIGFET devices. ISQED Jeferson José Baqueta, Felipe S. Marranghello, Vinicius N. Possani, Augusto Neutzling, André Inácio Reis, Renato P. Ribas
2017	J	`jnl`	SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. IEEE Trans. Emerg. Top. Comput. Vinícius Dal Bem, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2016	—	`conf`	Performance evaluation of optimized transistor networks built using independent-gate FinFET. LASCAS Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2015	C	`conf`	Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. ICCD Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2015	C	`conf`	Enhanced Spin-Diode Synthesis Using Logic Sharing. DSD Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis
2015	J	`jnl`	Factored Forms for Memristive Material Implication Stateful Logic. IEEE J. Emerg. Sel. Topics Circuits Syst. Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
2015	C	`conf`	Fast buffer delay estimation considering time-dependent dielectric breakdown. ISCAS Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2015	C	`conf`	Improved logic synthesis for memristive stateful logic using multi-memristor implication. ISCAS Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
2015	C	`conf`	SOP based logic synthesis for memristive IMPLY stateful logic. ICCD Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2014	C	`conf`	CMOS inverter analytical delay model considering all operating regions. ISCAS Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2013	—	`conf`	CMOS inverter delay model based on DC transfer curve for slow input. ISQED Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2013	—	`conf`	Delay model for static CMOS complex gates. SBCCI Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2013	—	`conf`	Spin diode network synthesis using functional composition. SBCCI Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis
2012	—	`conf`	Design-oriented delay model for CMOS inverter. SBCCI Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2011	C	`conf`	Impact and optimization of lithography-aware regular layout in digital circuit design. ICCD Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2011	—	`conf`	Transistor Sizing Analysis of Regular Fabrics. ARCS Workshops Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas, Francesc Moll
2011	—	`conf`	Transistor sizing in lithography-aware regular fabrics. SBCCI Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Francesc Moll, Renato P. Ribas