Felipe S. Marques

23 papers A 1C 3Journal 2Unranked 17
YearRankTypeTitle / Venue / Authors
2021 J jnl
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling.
ACM Trans. Design Autom. Electr. Syst.
Stephano Machado Moreira Goncalves, Leomar S. da Rosa Jr., Felipe S. Marques
2020 C conf
Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability.
ISCAS
Maicon Schneider Cardoso, Andrei A. O. Bubolz, Jordi Cortadella, Leomar Soares da Rosa Júnior, Felipe S. Marques
2019 C conf
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
ISCAS
Vitor G. Lima, Guilherme Paim, Leandro M. G. Rocha, Leomar S. da Rosa Jr., Felipe S. Marques, Eduardo A. C. da Costa, Vinícius V. Camargo, Rafael Soares, Sergio Bampi
2018 — conf
A Novel Sizing Method Aiming Security Against Differential Power Analysis.
ICECS
Vitor G. Lima, Plinio Finkenauer, Vinícius V. Camargo, Felipe S. Marques, Leomar Soares da Rosa Júnior, Rafael Iankowski Soares
2018 — conf
Area-Aware Design of Static CMOS Complex Gates.
NEWCAS
Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Leomar S. da Rosa Jr., Felipe S. Marques
2017 — conf
A post-processing methodology to improve the automatic design of CMOS gates at layout-level.
ICECS
Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
2017 C conf
Post-processing of supergate networks aiming cell layout optimization.
ISCAS
Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
2017 — conf
Simulated Annealing Applied to LUT-Based FPGA Technology Mapping.
MICAI (Special Session)
Matheus Nachtigall, Paulo Ferreira, Felipe S. Marques
2017 J jnl
Transistor Count Optimization in IG FinFET Network Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
2016 — conf
Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool.
LASCAS
Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa Jr.
2016 — conf
Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding.
MWSCAS
Gustavo H. Smaniotto, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa
2014 — conf
Exploring Independent Gates in FinFET-Based Transistor Network Generation.
SBCCI
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Júnior
2013 — conf
Improving the methodology to build non-series-parallel transistor arrangements.
SBCCI
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
2013 — conf
Transistor-level optimization of CMOS complex gates.
LASCAS
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2012 — conf
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.
SBCCI
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2012 — conf
Performance and Energy Consumption Analysis of Embedded Applications Based on Android Platform.
SBESC
Andrws Vieira, Daniel Debastiani, Luciano Volcan Agostini, Felipe S. Marques, Júlio C. B. de Mattos
2010 — conf
Improvements on the detection of false paths by using unateness and satisfiability.
SBCCI
Felipe S. Marques, Osvaldo Martinello, Renato P. Ribas, André Inácio Reis
2010 A conf
KL-Cuts: A new approach for logic synthesis targeting multiple output blocks.
DATE
Osvaldo Martinello, Felipe S. Marques, Renato P. Ribas, André Inácio Reis
2007 — conf
DAG based library-free technology mapping.
ACM Great Lakes Symposium on VLSI
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2006 — conf
Fast disjoint transistor networks from BDDs.
SBCCI
Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2005 — conf
A new approach to the use of satisfiability in false path detection.
ACM Great Lakes Symposium on VLSI
Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2002 — conf
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy.
SBCCI
Renato Fernandes Hentschke, Felipe S. Marques, Fernanda Lima, Luigi Carro, Altamiro Amadeu Susin, Ricardo Reis
2002 — conf
Testability Properties of BDDs.
SBCCI
Felipe S. Marques, Vinícius P. Correia, A. Prado, Marcelo Lubaszewski, André Inácio Reis