Felice Balarin

65 papers A* 13A 12B 1C 2Misc 3Journal 13Unranked 20

Year	Rank	Type	Title / Venue / Authors
2009	—	`conf`	Fast and accurate performance simulation of embedded software for MPSoC. ASP-DAC Eric Cheung, Harry Hsieh, Felice Balarin
2009	—	`conf`	Memory subsystem simulation in software TLM/T models. ASP-DAC Eric Cheung, Harry Hsieh, Felice Balarin
2009	—	`conf`	Partial order method for timed simulation of system-level MPSoC designs. ASP-DAC Eric Cheung, Harry Hsieh, Felice Balarin
2008	Misc	`conf`	Software optimization for MPSoC: a mpeg-2 decoder case study. CODES+ISSS Eric Cheung, Harry Hsieh, Felice Balarin
2007	J	`jnl`	Assertion-Based Design Exploration of DVS in Network Processor Architectures CoRR Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2007	—	`conf`	Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip. HLDVT Eric Cheung, Harry Hsieh, Felice Balarin
2007	—	`conf`	Framework for fast and accurate performance simulation of multiprocessor systems. HLDVT Eric Cheung, Harry Hsieh, Felice Balarin
2007	J	`jnl`	Specification, Synthesis, and Simulation of Transactor Processes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Felice Balarin, Roberto Passerone
2006	A	`conf`	Communication and co-simulation infrastructure for heterogeneous system integration. DATE Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli
2006	A	`conf`	Functional verification methodology based on formal interface specification and transactor generation. DATE Felice Balarin, Roberto Passerone
2006	J	`jnl`	Verification Approach of Metropolis Design Framework for Embedded Systems. Int. J. Parallel Program. Xi Chen, Harry Hsieh, Felice Balarin
2005	C	`conf`	A formal approach to system level design: metamodels and unified design environments. MEMOCODE Felice Balarin, Roberto Passerone, Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli
2005	A	`conf`	Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2004	J	`jnl`	Assertion Based Verification and Analysis of Network Processor Architectures. Des. Autom. Embed. Syst. Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
2004	—	`conf`	Assertion-based power/performance analysis of network processor architectures. HLDVT Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2004	J	`jnl`	Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2004	Misc	`conf`	Separation of concerns: overhead in modeling and efficient simulation techniques. EMSOFT Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin
2004	A	`conf`	Utilizing Formal Assertions for System Design of Network Processors. DATE Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
2003	A	`conf`	Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	A*	`conf`	Automatic trace analysis for logic of constraints. DAC Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	—	`conf`	Case Studies of Model Checking for Embedded System Designs. ACSD Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	J	`jnl`	Formal Verification for Embedded System Designs. Des. Autom. Embed. Syst. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	J	`jnl`	Metropolis: An Integrated Electronic System Design Environment. Computer Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli
2003	—	`ch.`	Simulation Trace Verification for Quantitative Constraints. Embedded Software for SoC Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	—	`conf`	Verifying LOC based functional and performance constraints. HLDVT Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2002	—	`conf`	Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. CODES Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang
2002	—	`conf`	Formal verification of embedded system designs at multiple levels of abstraction. HLDVT Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2002	—	`conf`	Modeling and Designing Heterogeneous Systems. Concurrency and Hardware Design Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe
2002	Misc	`conf`	Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. EMSOFT Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
2001	—	`conf`	Constraints specification at higher levels of abstraction. HLDVT Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
2001	—	`conf`	STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systems. CODES Felice Balarin
2001	—	`conf`	Scheduling Reactive Task Graphs in Embedded Control Systems. IEEE Real Time Technology and Applications Symposium Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin
2001	A	`conf`	Stars in VCC: Complementing Simulation with Worst-Case Analysis. ICCAD Felice Balarin
2001	J	`jnl`	Synchronous approach to the functional equivalence of embeddedsystem implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
2000	A	`conf`	Automatic Abstraction for Worst-Case Analysis of Discrete Systems. DATE Felice Balarin
2000	A*	`conf`	Efficient methods for embedded system design space exploration. DAC Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
2000	—	`conf`	Refining abstract equivalence analysis for embedded system design. HLDVT Harry Hsieh, Felice Balarin
2000	J	`jnl`	Sequential synthesis using S1S. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2000	A*	`conf`	Task scheduling with RT constraints. DAC Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin
1999	—	`conf`	Concurrent Symbolic Verification of Liveness Properties for Interleaved Models. SMC@FLoC Felice Balarin
1999	J	`jnl`	Equivalences for Fair Kripke Structures. Chic. J. Theor. Comput. Sci. Adnan Aziz, Felice Balarin, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1999	C	`conf`	Software Synthesis for Complex Reactive Embedded Systems. ICCD Felice Balarin, Massimiliano Chiodo
1999	A	`conf`	Synchronous equivalence for embedded systems: a tool for design exploration. ICCAD Harry Hsieh, Felice Balarin
1999	J	`jnl`	Synthesis of software programs for embedded control applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki
1999	—	`conf`	Worst-case analysis of discrete systems based on conditional abstractions. CODES Felice Balarin
1999	A	`conf`	Worst-case analysis of discrete systems. ICCAD Felice Balarin
1998	A*	`conf`	Correctness of the Concurrent Approach to Symbolic Verification of Interleaved Models. CAV Felice Balarin
1998	B	`conf`	Priority Assignment for Embedded Reactive Real-Time Systems. LCTES Felice Balarin
1998	J	`jnl`	Scheduling for Embedded Real-Time Systems. IEEE Des. Test Comput. Felice Balarin, Luciano Lavagno, Praveen K. Murthy, Alberto L. Sangiovanni-Vincentelli
1997	—	`conf`	Automatic Generation of a Real-Time Operating System for Embedded Systems. CODES Felice Balarin, Massimiliano Chiodo, Attila Jurecska, Luciano Lavagno, Bassam Tabbara, Alberto L. Sangiovanni-Vincentelli
1997	A*	`conf`	Schedule Validation for Embedded Reactive Real-Time Systems. DAC Felice Balarin, Alberto L. Sangiovanni-Vincentelli
1997	—	`conf`	Verifying invariants by approximate image computation. INFINITY Felice Balarin
1996	A	`conf`	Approximate reachability analysis of timed automata. RTSS Felice Balarin
1996	A*	`conf`	Formal Verification of Embedded Systems based on CFSM Networks. DAC Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
1995	J	`jnl`	An Iterative Approach to Verification of Real-Time Systems. Formal Methods Syst. Des. Felice Balarin, Alberto L. Sangiovanni-Vincentelli
1995	A*	`conf`	It Usually Works: The Temporal Logic of Stochastic Systems. CAV Adnan Aziz, Vigyan Singhal, Felice Balarin
1995	A	`conf`	Sequential synthesis using S1S. ICCAD Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1995	A*	`conf`	Supervisory Control of Finite State Machines. CAV Adnan Aziz, Felice Balarin, Robert K. Brayton, Marika Domenica Di Benedetto, Alexander Saldanha
1994	A*	`conf`	Equivalences for Fair Kripke Structures. ICALP Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A*	`conf`	HSIS: A BDD-Based Environment for Formal Verification. DAC Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A	`conf`	Iterative algorithms for formal verification of embedded real-time systems. ICCAD Felice Balarin, Alberto L. Sangiovanni-Vincentelli
1994	A*	`conf`	On the Automatic Computation of Network Invariants. CAV Felice Balarin, Alberto L. Sangiovanni-Vincentelli
1993	A*	`conf`	An Iterative Approach to Language Containment. CAV Felice Balarin, Alberto L. Sangiovanni-Vincentelli
1993	—	`conf`	Verilog HDL Modeling Styles for Formal Verification. CHDL Felice Balarin, Gary York
1992	A*	`conf`	A Verification Strategy for Timing-Constrained Systems. CAV Felice Balarin, Alberto L. Sangiovanni-Vincentelli