Fei Yuan - RankMe

119 papers B 2C 19Journal 41Unranked 57

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Comparative Study of Dynamic Comparators for Low-Power Successive Approximation ADC. IEEE Open J. Circuits Syst. Fei Yuan
2025	—	`conf`	Gated Delay Line Up-Down Counters for Mixed-Signal Processing. NewCAS Fei Yuan
2025	J	`jnl`	Sub-Threshold All-Digital DLL for Clock Generation of SAR ADC. IEEE Open J. Circuits Syst. Wenhao Wu, Fei Yuan, Yushi Zhou
2024	—	`conf`	A 0.6-V 108-nW 100-kHz Sub-Threshold Delay-Locked Loop with Digital Linearization for Low-Power SAR ADC. MWSCAS Wenhao Wu, Fei Yuan, Yushi Zhou
2024	—	`conf`	A Comparative Study of Dynamic Comparators in Low-Voltage SAR ADC. MWSCAS Fei Yuan
2024	C	`conf`	An 800 kS/s 1.83 fJ/conv. 12b ADC via Voltage Successive Approximation and Gated Cyclic Vernier Time Digitization. ISCAS Ian Perczak, Fei Yuan
2024	—	`conf`	Design Techniques for Sample-and-Hold with Bootstrapping in Low-Power SAR ADC. NewCAS Fei Yuan
2024	—	`conf`	Edge-Triggered Bi-Directional Gated Delay Line Up-Down Counters. MWSCAS Fei Yuan
2024	C	`conf`	Gated Ring Oscillator Time Amplifier with Pico-Second Sensitivity and Applications in All-Digital Variable-Gain Time Integrator. ISCAS Fei Yuan
2024	—	`conf`	Sub-Threshold Delay-Locked Loop with Piecewise Linearization and Time-Mode Proportional-Integral Locking. APCCAS Wenhao Wu, Fei Yuan, Yushi Zhou
2023	—	`conf`	A 3.97 µW 11.2b 500 kS/s Hybrid SAR ADC via Time-Mode Signal Processing. MWSCAS Ian Perczak, Fei Yuan
2023	—	`conf`	A Cyclic Vernier Digital-to-Time Converter for Time-Mode Successive Approximation TDC. MWSCAS Daniel Junehee Lee, Fei Yuan, Yushi Zhou
2023	C	`conf`	All-Digital Time Integrator with Bi-Directional Gated Ring Oscillator / Shift Register. ISCAS Fei Yuan
2023	J	`jnl`	Bi-Directional Gated Ring Oscillator Time Integrator. IEEE Trans. Circuits Syst. I Regul. Pap. Fei Yuan, Parth Parekh, Yushi Zhou
2023	—	`conf`	Gated Ring Oscillator Time Amplifier with Applications in Time Integration. NEWCAS Fei Yuan
2023	—	`conf`	Time-Interpolated Vernier Digital-to-Time Converter with Applications in Time-Mode SAR TDC. NEWCAS Daniel Junehee Lee, Fei Yuan, Yushi Zhou
2022	—	`conf`	All-Digital Bi-Directional Gated Ring Oscillator Time Integrator for Mixed-Mode Signal Processing. NEWCAS Parth Parekh, Fei Yuan, Yushi Zhou
2022	—	`conf`	Bi-Directional Gated Ring Oscillator Time Integrator for Time-Based Mixed-Signal Processing. MWSCAS Parth Parekh, Fei Yuan, Yushi Zhou
2022	J	`jnl`	Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter. Microelectron. J. Parth Parekh, Fei Yuan, Yushi Zhou
2022	J	`jnl`	Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Parth Parekh, Fei Yuan, Yushi Zhou
2022	C	`conf`	Metastability Correction Techniques for TSPC-DFF with Applications in Vernier TDC. ISCAS Fei Yuan
2022	J	`jnl`	Metastability Error Correction for True Single-Phase Clock DFF With Applications in Vernier TDC. IEEE Trans. Circuits Syst. II Express Briefs Fei Yuan
2022	—	`conf`	Performance Limits of Gated Delay Line Time Integrators. CCECE Fei Yuan
2021	J	`jnl`	Adaptive data-transition decision feedback equaliser with edge emphasis. IET Circuits Devices Syst. Yue Li, Fei Yuan
2021	C	`conf`	All-Digital Successive Approximation TDC in Time-Mode Signal Processing. ISCAS Daniel Junehee Lee, Fei Yuan, Yushi Zhou
2021	J	`jnl`	All-digital successive approximation TDC in time-mode signal processing. Microelectron. J. Daniel Junehee Lee, Fei Yuan, Yushi Zhou
2021	J	`jnl`	An 8-bit digital-to-time converter with pre-skewing and time interpolation. IET Circuits Devices Syst. Daniel Junehee Lee, Fei Yuan, Gul N. Khan, Yushi Zhou
2021	—	`conf`	Bootstrapping Techniques for Energy-Efficient SAR ADCs : A State-of-the-Art Review. MWSCAS Fei Yuan
2021	—	`conf`	Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing. MWSCAS Parth Parekh, Fei Yuan, Yushi Zhou
2021	—	`conf`	Successive Approximation Register TDC in Time-Mode Signal Processing. MWSCAS Daniel Junehee Lee, Fei Yuan, Yushi Zhou
2020	—	`conf`	All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line. MWSCAS Parth Parekh, Fei Yuan, Yushi Zhou
2020	J	`jnl`	All-digital power-efficient integrating frequency difference-to-digital converter for GHz frequency-locking. IET Circuits Devices Syst. Yue Li, Fei Yuan
2020	J	`jnl`	Analysis and Design of an All-Digital ∆Σ TDC via Time-Mode Signal Processing. IEEE Trans. Circuits Syst. II Express Briefs Fei Yuan, Parth Parekh
2020	—	`conf`	Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability. MWSCAS Parth Parekh, Fei Yuan, Yushi Zhou
2020	J	`jnl`	Time-based all-digital Δ Σ time-to-digital converter with pre-skewed bi-directional gated delay line time integrator. IET Circuits Devices Syst. Fei Yuan, Parth Parekh
2019	—	`conf`	A 500-MS/s 8.4-ps Double-Edge Successive Approximation TDC in 65 nm CMOS. MWSCAS Rashed Siddiqui, Fei Yuan, Yushi Zhou
2019	—	`conf`	A Pre-Skewed Bi-Directional Gated Delay Line Bang-Bang Frequency Detector with Applications in 10 Gbps Serial Link Frequency-Locking. MWSCAS Yue Li, Fei Yuan
2019	—	`conf`	All-Digital ∆Σ TDC with Current-Starved Bi-Directional Gated Delay Line Time Integrator. MWSCAS Fei Yuan, Parth Parekh
2019	—	`conf`	Data-Transition Decision Feedback Equalizer with Edge-Emphasis Taps and Raised References. NEWCAS Yue Li, Fei Yuan
2019	—	`conf`	Digitally Interpolated Pre-Skewed Delay-Line Digital-to-Time Converter with Minimum Nonlinearity and Latency. MWSCAS Daniel Junehee Lee, Fei Yuan, Gul N. Khan
2019	J	`jnl`	Sign IET Circuits Devices Syst. Yue Li, Fei Yuan
2019	—	`conf`	Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration. MWSCAS Fei Yuan, Parth Parekh
2018	—	`conf`	A Comparative Study Of Injection Locked Frequency Divider Using Harmonic Mixer In Weak And Strong Inversion. MWSCAS Yushi Zhou, Jared Mercier, Fei Yuan
2018	J	`jnl`	All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator. Microelectron. J. Young Jun Park, Parth Parekh, Fei Yuan
2018	—	`conf`	Data-Transition Decision Feedback Equalizer with S NEWCAS Yue Li, Fei Yuan
2018	J	`jnl`	Design techniques of all-digital arithmetic units for time-mode signal processing. IET Circuits Devices Syst. Fei Yuan
2018	—	`conf`	Multi-Swarm based NoC Configuration and Synthesis. NORCAS Muhammad Obaidullah, Gul N. Khan, Fei Yuan
2018	—	`conf`	Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator. NEWCAS Parth Parekh, Fei Yuan
2017	—	`conf`	1-1 MASH ΔΣ time-to-digital converter with differential cascode time integrator. MWSCAS Young Jun Park, Fei Yuan
2017	—	`conf`	Adaptive 4PAM decision feedback equalizer with reduced number of slicers. MWSCAS Yushi Zhou, Fei Yuan
2017	—	`conf`	Adaptive data-transition decision feedback equalizer for serial links. MWSCAS Yue Li, Fei Yuan
2017	—	`conf`	All-digital ΔΣ TDC with differential bi-directional gated-delay-line time integrator. MWSCAS Young Jun Park, Fei Yuan
2017	—	`conf`	An adaptive edge decision feedback equalizer with 4PAM signalling. MWSCAS Matthew Dolan, Fei Yuan
2017	—	`conf`	Data-transition adaptive decision feedback equalizer for 2/4PAM serial links. MWSCAS Yue Li, Fei Yuan
2017	—	`conf`	Low-power all-digital ΔΣ TDC with bi-directional gated delay line time integrator. MWSCAS Young Jun Park, Fei Yuan
2017	J	`jnl`	Two-step pulse-shrinking time-to-digital converter. Microelectron. J. Young Jun Park, Fei Yuan
2016	—	`conf`	A phasor-domain study of injection-locking of harmonic oscillators with multiple injections. NEWCAS Fei Yuan
2016	J	`jnl`	Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection. Circuits Syst. Signal Process. Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye
2016	J	`jnl`	Calibration Technique for Maximum Power Harvest of Passive Wireless Microsystems. Circuits Syst. Signal Process. Xiongliang Lai, Fei Yuan
2016	—	`conf`	Data transient insensitive phase-locked loops. NEWCAS Durand Jarrett-Amor, Fei Yuan
2016	C	`conf`	Time integrator for mixed-mode signal processing. ISCAS Young Jun Park, Durand Jarrett-Amor, Fei Yuan
2016	C	`conf`	Time-mode techniques for fast-locking phase-locked loops. ISCAS Durand Jarrett-Amor, Young Jun Park, Fei Yuan
2015	—	`conf`	0.25-4 ns 185 MS/s 4-bit pulse-shrinking time-to-digital converter in 130 nm CMOS using a 2-step conversion scheme. MWSCAS Young Jun Park, Fei Yuan
2015	—	`conf`	A 12.88 MS/s 0.28 pJ/conv.step 8-bit stage-interleaved pulse-shrinking time-to-digital converter in 130 nm CMOS. MWSCAS Young Jun Park, Fei Yuan
2015	J	`jnl`	A Quadrature Charge-Domain Sampling Mixer With Embedded FIR, IIR, and N-Path Filters. IEEE Trans. Circuits Syst. I Regul. Pap. Yushi Zhou, Norman M. Filiol, Fei Yuan
2015	C	`conf`	Minimum jitter adaptive decision feedback equalizer for 4PAM serial links. ISCAS Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye
2015	J	`jnl`	Study of injection-locked non-harmonic oscillators using Volterra series. IET Circuits Devices Syst. Yushi Zhou, Fei Yuan
2014	C	`conf`	A new adaptive Decision Feedback Equalizer using hexagon eye-opening monitor for multi Gbps data links. ISCAS Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye
2014	J	`jnl`	New 2-D Eye-Opening Monitor for Gb/s Serial Links. IEEE Trans. Very Large Scale Integr. Syst. Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye, Saman Sadr
2013	J	`jnl`	Frequency-Domain Study of Lock Range of Non-Harmonic Oscillators With Multiple Multi-Tone Injections. IEEE Trans. Circuits Syst. I Regul. Pap. Fei Yuan, Yushi Zhou
2013	—	`conf`	Hardware realization of GALS based cortical column systems. AHS Anita Tino, Gul N. Khan, Fei Yuan
2013	C	`conf`	Low-power programmable charge-domain sampler with embedded N-path bandpass filter for software-defined radio. ISCAS Yushi Zhou, Norm M. Filiol, Shaul Peker, Fei Yuan
2013	J	`jnl`	Passive voltage shifters for analogue signaling. IET Circuits Devices Syst. Xiongliang Lai, Fei Yuan
2013	—	`conf`	Remote calibration of wireless power harvest. MWSCAS Xiongliang Lai, Fei Yuan
2013	B	`conf`	Towards Hardware Realizations of Intelligent Systems: A Cortical Column Approach. ICPP Anita Tino, Gul N. Khan, Fei Yuan
2013	—	`conf`	Two-dimensional eye-opening monitor for serial links. MWSCAS Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye
2012	J	`jnl`	A Phasor-Domain Study of Lock Range of Harmonic Oscillators With Multiple Injections. IEEE Trans. Circuits Syst. II Express Briefs Fei Yuan, Yushi Zhou
2012	—	`conf`	A frequency-domain study of lock range of harmonic oscillators with multiple injections. NEWCAS Fei Yuan, Yushi Zhou
2012	—	`conf`	Passive voltage level shifters for analog signaling. NEWCAS Xiongliang Lai, Fei Yuan
2011	J	`jnl`	A Study of the Lock Range of Injection-Locked CMOS Active-Inductor Oscillators Using a Linear Control System Approach. IEEE Trans. Circuits Syst. II Express Briefs Yushi Zhou, Fei Yuan
2011	B	`conf`	XTEA Based Secure Authentication Protocol for RFID Systems. ICCCN Gul N. Khan, Jack Yu, Fei Yuan
2011	—	`conf`	XTEA encryption based novel RFID security protocol. CCECE Jack Yu, Gul N. Khan, Fei Yuan
2010	J	`jnl`	A High-Gain Power-Matching Technique for Efficient Radio-Frequency Power Harvest of Passive Wireless Microsystems. IEEE Trans. Circuits Syst. I Regul. Pap. Nima Soltani, Fei Yuan
2010	J	`jnl`	A step-up transformer impedance transformation technique for efficient power harvesting of passive transponders. Microelectron. J. Nima Soltani, Fei Yuan
2010	J	`jnl`	Nonharmonic Injection-Locked Phase-Locked Loops With Applications in Remote Frequency Calibration of Passive Wireless Transponders. IEEE Trans. Circuits Syst. I Regul. Pap. Nima Soltani, Fei Yuan
2009	C	`conf`	A Wide Frequency Tuning Range Active-inductor Voltage-controlled Oscillator for Ultra Wideband Applications. ISCAS Dominic DiClemente, Fei Yuan
2009	J	`jnl`	A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification. Microelectron. J. Yong Chen, Fei Yuan, Gul N. Khan
2009	J	`jnl`	Inter-signal timing skew compensation of parallel links with current-mode incremental signalling. IET Circuits Devices Syst. An Hu, Fei Yuan
2009	J	`jnl`	Intersignal Timing Skew Compensation of Parallel Links With Voltage-Mode Incremental Signaling. IEEE Trans. Circuits Syst. I Regul. Pap. An Hu, Fei Yuan
2009	J	`jnl`	Parallel links with current-mode incremental signaling and per-pin skew compensation. Microelectron. J. An Hu, Fei Yuan
2009	C	`conf`	Remote Frequency Calibration of Passive Wireless Microsensors and Transponders using Injection-locked Phase-locked Loop. ISCAS Nima Soltani, Fei Yuan
2008	J	`jnl`	A New CMOS Active Transformer QPSK Modulator With Optimal Bandwidth Control. IEEE Trans. Circuits Syst. II Express Briefs Adrian Tang, Fei Yuan, Eddie Law
2008	C	`conf`	A new WiMAX sigma-delta modulator with constant-Q active inductors. ISCAS Adrian Tang, Fei Yuan, Eddie Law
2008	J	`jnl`	CMOS current-mode integrating receivers for Gbytes/s parallel links. Microelectron. J. Fei Yuan, Tao Wang
2008	J	`jnl`	Current-Mode Phase-Locked Loops With CMOS Active Transformers. IEEE Trans. Circuits Syst. II Express Briefs Dominic DiClemente, Fei Yuan, Adrian Tang
2008	C	`conf`	Inter-signal timing skew compensation of parallel links with voltage-mode incremental signaling. ISCAS An Hu, Fei Yuan
2007	C	`conf`	A New CMOS BPSK Modulator with Optimal Transaction Bandwidth Control. ISCAS Adrian Tang, Fei Yuan, Eddie Law
2007	J	`jnl`	A New Current-Mode Incremental Signaling Scheme With Applications to Gb/s Parallel Links. IEEE Trans. Circuits Syst. I Regul. Pap. Tao Wang, Fei Yuan
2007	C	`conf`	CMOS Gyrator-C Active Transformers. ISCAS Fei Yuan
2007	J	`jnl`	CMOS gyrator-C active transformers. IET Circuits Devices Syst. Fei Yuan
2007	J	`jnl`	Current-Mode Phase-Locked Loops - A New Architecture. IEEE Trans. Circuits Syst. II Express Briefs Dominic DiClemente, Fei Yuan
2007	C	`conf`	Current-Mode Phase-Locked Loops with Low Supply Voltage Sensitivity. ISCAS Dominic DiClemente, Fei Yuan
2006	—	`conf`	A 0.13 ACM Great Lakes Symposium on VLSI Minghai Li, Fei Yuan
2006	C	`conf`	A new area-efficient 4-PAM 10 Gb/s CMOS serial link transmitter. ISCAS Fei Yuan, Minghai Li
2006	C	`conf`	A new current-mode incremental signaling scheme with applications to Gb/s parallel links. ISCAS Tao Wang, Fei Yuan
2006	—	`conf`	A new power-area efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10Gb/s serial links. ACM Great Lakes Symposium on VLSI Fei Yuan
2006	J	`jnl`	Low-voltage CMOS current-mode preamplifier: analysis and design. IEEE Trans. Circuits Syst. I Regul. Pap. Fei Yuan
2005	J	`jnl`	0.18µm CMOS 10-Gb/s Current-Mode Serial Link Transmitters. IEICE Trans. Inf. Syst. Fei Yuan, Jean Jiang
2004	—	`conf`	Inductive peaking in wideband CMOS current amplifiers. ISCAS (4) Bendong Sun, Fei Yuan, Ajoy Opal
2003	—	`conf`	A new differential CMOS current pre-amplifier for optical communications. ISCAS (1) Bendong Sun, Fei Yuan
2003	—	`conf`	Low voltage, low power operational amplifier. ICECS Shahab Ardalan, Kaamran Raahemifar, Fei Yuan
2003	—	`conf`	Time domain response and sensitivity of periodically switched nonlinear circuits. ISCAS (4) Quan Li, Fei Yuan
2002	J	`jnl`	An efficient transient analysis algorithm for mildly nonlinearcircuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Yuan, Ajoy Opal
2002	—	`conf`	An overview of design techniques for CMOS phase detectors. ISCAS (5) Sameh Soliman, Fei Yuan, Kaamran Raahemifar
2002	—	`conf`	Statistical analysis of switched linear networks. ISCAS (1) Fei Yuan
2001	—	`conf`	A new initialization technique in designing and testing phases of asynchronous circuits. ICECS Kaamran Raahemifar, Fei Yuan, Farahnaz A. Mohammadi
2001	—	`conf`	Efficient transient analysis of nonlinear circuits using Volterra series and piecewise constant interpolation. ISCAS (3) Fei Yuan, Kaamran Raahemifar, Farahnaz A. Mohammadi
1999	—	`conf`	Distortion analysis of periodically switched nonlinear circuits. ISCAS (5) Fei Yuan, Ajoy Opal
1999	—	`conf`	Sensitivity analysis of periodically switched linear circuits using an adjoint network technique. ISCAS (5) Fei Yuan, Ajoy Opal