Fei Lyu - RankMe

16 papers C 2Journal 13Unranked 1

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	SMOTrojan: A golden model-free GNN-SMOTE framework for automated Hardware Trojan detection via synthetic node-edge synthesis. Microelectron. J. Fei Lyu, Zilong Su, Sen Wang, Chenghua Wang, Yijun Cui, Weiqiang Liu
2025	J	`jnl`	A Universal Methodology of Complex Number Computation for Low-Complexity and High-Speed Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. Yu Wang, Jin Zhang, Youlong Wu, Fei Lyu, Yuanyong Luo
2025	J	`jnl`	An Efficient Methodology for Binary Logarithmic Computations of Floating-Point Numbers With Normalized Output Within One ulp of Accuracy. IEEE Trans. Computers Fei Lyu, Yuanyong Luo, Weiqiang Liu
2024	C	`conf`	An Optimized Architecture for Computing the Square Root of Complex Numbers. ISCAS Yu Wang, Haoyu Zhang, Wei Hu, Xin Zhang, Xinyu Tian, Fei Lyu, Yuanyong Luo
2024	J	`jnl`	FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation. IEEE Trans. Circuits Syst. II Express Briefs Yu Wang, Xingcheng Liang, Shuai Niu, Chi Zhang, Fei Lyu, Yuanyong Luo
2022	J	`jnl`	A New Design of a CMOS Vertical Hall Sensor with a Low Offset. Sensors Fei Lyu, Shuo Huang, Chaoran Wu, Xingcheng Liang, Pengzhan Zhang, Yuxuan Wang, Hongbing Pan, Yu Wang
2022	J	`jnl`	An optimized hardware implementation of the CORDIC algorithm. IEICE Electron. Express Fei Lyu, Chaoran Wu, Yuxuan Wang, Hongbing Pan, Yu Wang, Yuanyong Luo
2022	J	`jnl`	High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers. IEEE Trans. Very Large Scale Integr. Syst. Fei Lyu, Yan Xia, Yuheng Chen, Yanxu Wang, Yuanyong Luo, Yu Wang
2022	J	`jnl`	ML-PLAC: Multiplierless Piecewise Linear Approximation for Nonlinear Function Evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. Fei Lyu, Yan Xia, Zhelong Mao, Yanxu Wang, Yu Wang, Yuanyong Luo
2022	C	`conf`	Reconfigurable Multifunction Computing Unit Using an Universal Piecewise Linear Method. ISCAS Fei Lyu, Jian Chen, Shuo Huang, Wenxiu Wang, Yuanyong Luo, Yu Wang
2021	J	`jnl`	PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers. IEEE Trans. Very Large Scale Integr. Syst. Fei Lyu, Zhelong Mao, Jin Zhang, Yu Wang, Yuanyong Luo
2021	J	`jnl`	Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers. IEEE Trans. Circuits Syst. I Regul. Pap. Fei Lyu, Xiaoqi Xu, Yu Wang, Yuanyong Luo, Yuxuan Wang, Hongbing Pan
2018	J	`jnl`	A New Design of a Single-Device 3D Hall Sensor: Cross-Shaped 3D Hall Sensor. Sensors Wei Tang, Fei Lyu, Dunhui Wang, Hongbing Pan
2016	J	`jnl`	Influences of an Aluminum Covering Layer on the Performance of Cross-Like Hall Devices. Sensors Fei Lyu, Xinfu Liu, Yinjie Ding, Eng-Huat Toh, Zhenyan Zhang, Yifan Pan, Zhen Wang, Chengjie Li, Li Li, Jin Sha, Hongbing Pan
2015	J	`jnl`	Performance Comparison of Cross-Like Hall Plates with Different Covering Layers. Sensors Fei Lyu, Zhenyan Zhang, Eng-Huat Toh, Xinfu Liu, Yinjie Ding, Yifan Pan, Chengjie Li, Li Li, Jin Sha, Hongbing Pan
2014	—	`conf`	A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs. ISIC Fei Lyu, Zhenduo Zhu, Zhenfei Lu, Li Li, Jin Sha, Hongbing Pan, Yutong Bi