Fazal Hameed

37 papers A* 2A 7B 1Misc 2Journal 21Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
An Efficient Racetrack Cache Architecture for Performance-Area-Energy Co-Optimization.
IEEE Access
Fazal Hameed
2025 J jnl
Scalability and Limitations of Existing Software Requirements Prioritization Techniques: A Systematic Literature Review.
J. Softw. Evol. Process.
Muhammad Yaseen, Waqar Mehmood, Fazal Hameed, Muhammad Asif Nauman
2024 J jnl
Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory.
IEEE Comput. Archit. Lett.
Asif Ali Khan, Fazal Hameed, Taha Shahroodi, Alex K. Jones, Jerónimo Castrillón
2023 J jnl
An energy-efficient cache replacement policy for ultra-dense racetrack memory.
J. Syst. Archit.
Fazal Hameed, Moazam Maqsood, Syed Ali Irtaza
2023 J jnl
DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories.
IEEE Trans. Computers
Asif Ali Khan, Sébastien Ollivier, Fazal Hameed, Jerónimo Castrillón, Alex K. Jones
2023 J jnl
ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees.
IEEE Trans. Computers
Christian Hakert, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jerónimo Castrillón, Jian-Jia Chen
2022 J jnl
ALPHA: A Novel Algorithm-Hardware Co-Design for Accelerating DNA Seed Location Filtering.
IEEE Trans. Emerg. Top. Comput.
Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón
2022 J jnl
BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fazal Hameed, Jerónimo Castrillón
2022 J jnl
DNA Pre-Alignment Filter Using Processing Near Racetrack Memory.
IEEE Comput. Archit. Lett.
Fazal Hameed, Asif Ali Khan, Sébastien Ollivier, Alex K. Jones, Jerónimo Castrillón
2022 J jnl
DNA Pre-alignment Filter using Processing Near Racetrack Memory.
CoRR
Fazal Hameed, Asif Ali Khan, Sébastien Ollivier, Alex K. Jones, Jerónimo Castrillón
2021 A* conf
BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory.
DAC
Christian Hakert, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jerónimo Castrillón, Jian-Jia Chen
2021 J jnl
Improving the Performance of Block-based DRAM Caches Via Tag-Data Decoupling.
IEEE Trans. Computers
Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón
2020 A conf
Generalized Data Placement Strategies for Racetrack Memories.
DATE
Asif Ali Khan, Andrés Goens, Fazal Hameed, Jerónimo Castrillón
2020 J jnl
Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade.
Proc. IEEE
Robin Bläsing, Asif Ali Khan, Panagiotis Ch. Filippou, Chirag Garg, Fazal Hameed, Jerónimo Castrillón, Stuart S. P. Parkin
2020 J jnl
Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories.
ACM Trans. Embed. Comput. Syst.
Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jerónimo Castrillón
2020 J jnl
ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0.
ACM Trans. Archit. Code Optim.
Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón
2019 J jnl
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement.
IEEE Trans. Very Large Scale Integr. Syst.
Fazal Hameed, Jerónimo Castrillón
2019 J jnl
Generalized Data Placement Strategies for Racetrack Memories.
CoRR
Asif Ali Khan, Andres Goens, Fazal Hameed, Jerónimo Castrillón
2019 B conf
Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads.
LCTES
Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jerónimo Castrillón
2019 J jnl
RTSim: A Cycle-Accurate Simulator for Racetrack Memories.
IEEE Comput. Archit. Lett.
Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón
2019 A conf
SHRIMP: Efficient Instruction Delivery with Domain Wall Memory.
ISLPED
Joonas Multanen, Pekka Jääskeläinen, Asif Ali Khan, Fazal Hameed, Jerónimo Castrillón
2019 J jnl
ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0.
CoRR
Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón
2018 — conf
NVMain Extension for Multi-Level Cache Systems.
RAPIDO
Asif Ali Khan, Fazal Hameed, Jerónimo Castrillón
2018 J jnl
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache.
IEEE Trans. Very Large Scale Integr. Syst.
Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón
2018 J jnl
VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, Mehdi Baradaran Tahoori
2017 — conf
Efficient STT-RAM last-level-cache architecture to replace DRAM cache.
MEMSYS
Fazal Hameed, Christian Menard, Jerónimo Castrillón
2017 A conf
Rethinking on-chip DRAM cache for simultaneous performance and energy optimization.
DATE
Fazal Hameed, Jerónimo Castrillón
2016 J jnl
Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fazal Hameed, Lars Bauer, Jörg Henkel
2016 — conf
Architecting STT Last-Level-Cache for performance and energy improvement.
ISQED
Fazal Hameed, Mehdi Baradaran Tahoori
2016 A conf
Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches.
ISLPED
Fabian Oboril, Fazal Hameed, Rajendra Bishnoi, Ali Ahari, Helia Naeimi, Mehdi Baradaran Tahoori
2015 — —
DRAM Aware Last-Level-Cache Policies for Multi-core Systems.
Fazal Hameed
2014 A* conf
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture.
DAC
Fazal Hameed, Lars Bauer, Jörg Henkel
2013 A conf
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores.
DATE
Fazal Hameed, Lars Bauer, Jörg Henkel
2013 Misc conf
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache.
CODES+ISSS
Fazal Hameed, Lars Bauer, Jörg Henkel
2013 Misc conf
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies.
CASES
Fazal Hameed, Lars Bauer, Jörg Henkel
2012 A conf
Dynamic cache management in multi-core architectures through run-time adaptation.
DATE
Fazal Hameed, Lars Bauer, Jörg Henkel
2011 A conf
Dynamic thermal management in 3D multi-core architecture through run-time adaptation.
DATE
Fazal Hameed, Mohammad Abdullah Al Faruque, Jörg Henkel