Farid N. Najm

154 papers A* 30A 47C 3Journal 49Unranked 24
YearRankTypeTitle / Venue / Authors
2025 J jnl
Novel Partitioning-Based Approach for Electromigration Assessment With Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tianshu Hou, Farid N. Najm, Ngai Wong, Hai-Bao Chen
2024 — conf
Fast Current Constraints Generation for Chip Safety.
ISQED
Cedric Feghali, Farid N. Najm
2023 — conf
Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution.
ISPD
Armen Kteyan, Valeriy Sukharev, Alexander Volkov, Jun-Ho Choy, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Stéphane Moreau
2023 — conf
Fast Electromigration Simulation for Chip Power Grids.
ISQED
Bijan Shahriari, Farid N. Najm
2022 J jnl
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Valeriy Sukharev, Armen Kteyan, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Jun-Ho Choy, Sofya Torosyan, Yu Zhu
2020 A conf
Electromigration Checking Using a Stochastic Effective Current Model.
ICCAD
Adam Issa, Valeriy Sukharev, Farid N. Najm
2019 — conf
Efficient Simulation of Electromigration Damage in Large Chip Power Grids Using Accurate Physical Models (Invited Paper).
IRPS
Farid N. Najm, Valeriy Sukharev
2019 A conf
Power Grid Fixing for Electromigration-induced Voltage Failures.
ICCAD
Zahi Moudallal, Valeriy Sukharev, Farid N. Najm
2019 J jnl
Power Scheduling With Active RC Power Grids.
IEEE Trans. Very Large Scale Integr. Syst.
Zahi Moudallal, Farid N. Najm
2018 J jnl
Power Grid Electromigration Checking Using Physics-Based Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm
2017 J jnl
Fast Vectorless RLC Grid Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohammad Fawaz, Farid N. Najm
2017 A conf
Fast physics-based electromigration assessment by efficient solution of linear time-invariant (LTI) systems.
ICCAD
Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm
2017 J jnl
Generating Current Constraints to Guarantee RLC Power Grid Safety.
ACM Trans. Design Autom. Electr. Syst.
Zahi Moudallal, Farid N. Najm
2017 — conf
Parallel Simulation-Based Verification of RC Power Grids.
ISVLSI
Mohammad Fawaz, Farid N. Najm
2017 A conf
Power grid verification under transient constraints.
ICCAD
Mohammad Fawaz, Farid N. Najm
2017 A conf
Power scheduling with active power grids.
ICCAD
Zahi Moudallal, Farid N. Najm
2016 A conf
A fast layer elimination approach for power grid reduction.
ICCAD
Abdul-Amir Yassine, Farid N. Najm
2016 A conf
Accurate verification of RC power grids.
DATE
Mohammad Fawaz, Farid N. Najm
2016 A conf
Fast physics-based electromigration checking for on-die power grids.
ICCAD
Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm
2016 — conf
Fast simulation-based verification of RC power grids.
CCECE
Mohammad Fawaz, Farid N. Najm
2016 J jnl
Generating Current Budgets to Guarantee Power Grid Safety.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zahi Moudallal, Farid N. Najm
2016 C conf
Generating voltage drop aware current budgets for RC power grids.
ISCAS
Zahi Moudallal, Farid N. Najm
2016 J jnl
Verification of the Power and Ground Grids Under General and Hierarchical Constraints.
IEEE Trans. Very Large Scale Integr. Syst.
Mehmet Avci, Farid N. Najm
2015 — conf
Generating circuit current constraints to guarantee power grid safety.
ASP-DAC
Zahi Moudallal, Farid N. Najm
2015 — conf
Physical Design Challenges in the Chip Power Distribution Network.
ISPD
Farid N. Najm
2015 J jnl
Redundancy-Aware Power Grid Electromigration Checking Under Workload Uncertainties.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sandeep Chatterjee, Mohammad Fawaz, Farid N. Najm
2013 A conf
A vectorless framework for power grid electromigration checking.
ICCAD
Mohammad Fawaz, Sandeep Chatterjee, Farid N. Najm
2013 A conf
Redundancy-aware electromigration checking for mesh power grids.
ICCAD
Sandeep Chatterjee, Mohammad Fawaz, Farid N. Najm
2012 J jnl
Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Khaled R. Heloue, Sari Onaissi, Farid N. Najm
2012 A* conf
Incremental power grid verification.
DAC
Abhishek, Farid N. Najm
2012 J jnl
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm
2012 A conf
Overview of vectorless/early power grid verification.
ICCAD
Farid N. Najm
2011 A* conf
A fast approach for static timing analysis covering all PVT corners.
DAC
Sari Onaissi, Feroze Taraporevala, Jinfeng Liu, Farid N. Najm
2011 A conf
Efficient RC power grid verification using node elimination.
DATE
Ankit Goyal, Farid N. Najm
2011 J jnl
Fast Vectorless Power Grid Verification Under an RLC Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nahi H. Abdul Ghani, Farid N. Najm
2011 A* conf
Power grid correction using sensitivity analysis under an RC model.
DAC
Pamela Al Haddad, Farid N. Najm
2011 A* conf
Power grid verification using node and branch dominance.
DAC
Nahi H. Abdul Ghani, Farid N. Najm
2010 A conf
Early P/G grid voltage integrity verification.
ICCAD
Mehmet Avci, Farid N. Najm
2010 — conf
Managing verification error traces with bounded model debugging.
ASP-DAC
Sean Safarpour, Andreas G. Veneris, Farid N. Najm
2010 A conf
Power grid correction using sensitivity analysis.
ICCAD
Meric Aydonat, Farid N. Najm
2010 J jnl
Verification and Codesign of the Package and Die Power Delivery System Using Wavelets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Imad A. Ferzli, Eli Chiprout, Farid N. Najm
2009 A* conf
Clock skew optimization via wiresizing for timing sign-off covering all process corners.
DAC
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
2009 A* conf
Fast vectorless power grid verification using an approximate inverse technique.
DAC
Nahi H. Abdul Ghani, Farid N. Najm
2009 J jnl
Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Khaled R. Heloue, Navid Azizi, Farid N. Najm
2009 J jnl
Low-Power Programmable FPGA Routing Circuitry.
IEEE Trans. Very Large Scale Integr. Syst.
Jason Helge Anderson, Farid N. Najm
2009 A conf
PSTA-based branch and bound approach to the silicon speedpath isolation problem.
ICCAD
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
2009 A conf
Quantifying robustness metrics in parameterized static timing analysis.
ICCAD
Khaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm
2008 J jnl
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sari Onaissi, Farid N. Najm
2008 J jnl
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Khaled R. Heloue, Farid N. Najm
2008 A conf
Efficient block-based parameterized timing analysis covering all potentially critical paths.
ICCAD
Khaled R. Heloue, Sari Onaissi, Farid N. Najm
2008 A* conf
Parameterized timing analysis with general delay models and arbitrary variation sources.
DAC
Khaled R. Heloue, Farid N. Najm
2007 J jnl
A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farid N. Najm, Noel Menezes, Imad A. Ferzli
2007 A conf
A geometric approach for early power grid verification using current constraints.
ICCAD
Imad A. Ferzli, Farid N. Najm, Lars Kruse
2007 A conf
Early power grid verification under circuit current uncertainties.
ISLPED
Imad A. Ferzli, Farid N. Najm, Lars Kruse
2007 A conf
Maximum circuit activity estimation using pseudo-boolean satisfiability.
DATE
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
2007 A* conf
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation.
DAC
Khaled R. Heloue, Navid Azizi, Farid N. Najm
2007 J jnl
Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst.
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
2006 — conf
A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme.
CICC
Kostas Pagiamtzis, Navid Azizi, Farid N. Najm
2006 A* conf
A family of cells to reduce the soft-error-rate in ternary-CAM.
DAC
Navid Azizi, Farid N. Najm
2006 A conf
A linear-time approach for static timing analysis covering all process corners.
ICCAD
Sari Onaissi, Farid N. Najm
2006 J jnl
Active leakage power optimization for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jason Helge Anderson, Farid N. Najm
2006 A* conf
An adaptive FPGA architecture with process variation compensation and reduced leakage.
DAC
Georges Nabaa, Navid Azizi, Farid N. Najm
2006 J jnl
Analysis and verification of power grids considering process-induced leakage-current variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Imad A. Ferzli, Farid N. Najm
2006 J jnl
Dynamic-range estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bin Wu, Jianwen Zhu, Farid N. Najm
2006 A conf
Handling inductance in early power grid verification.
ICCAD
Nahi H. Abdul Ghani, Farid N. Najm
2006 J jnl
High-level current macro model for logic blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Srinivas Bodapati, Farid N. Najm
2006 J jnl
Voltage-Aware Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
2005 J jnl
A Case for Asymmetric-Cell Cache Memories.
IEEE Trans. Very Large Scale Integr. Syst.
Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi
2005 A* conf
A non-parametric approach for dynamic range estimation of nonlinear systems.
DAC
Bin Wu, Jianwen Zhu, Farid N. Najm
2005 J jnl
Early power estimation for VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kavel M. Büyüksahin, Farid N. Najm
2005 A conf
Incremental partitioning-based vectorless power grid verification.
ICCAD
Dionysios Kouroussis, Imad A. Ferzli, Farid N. Najm
2005 — conf
Leakage power: trends, analysis and avoidance.
ASP-DAC
David T. Blaauw, Anirudh Devgan, Farid N. Najm
2005 — conf
Look-up table leakage reduction for FPGAs.
CICC
Navid Azizi, Farid N. Najm
2005 A* conf
On the need for statistical timing analysis.
DAC
Farid N. Najm
2005 A conf
Power grid voltage integrity verification.
ISLPED
Maha Nizam, Farid N. Najm, Anirudh Devgan
2005 A conf
Statistical timing analysis with two-sided constraints.
ICCAD
Khaled R. Heloue, Farid N. Najm
2005 A* conf
Variations-aware low-power design with voltage scaling.
DAC
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
2004 — conf
A novel low-power FPGA routing switch.
CICC
Jason Helge Anderson, Farid N. Najm
2004 A conf
Active leakage power optimization for FPGAs.
FPGA
Jason Helge Anderson, Farid N. Najm, Tim Tuan
2004 — conf
An Asymmetric SRAM Cell to Lower Gate Leakage.
ISQED
Navid Azizi, Farid N. Najm
2004 A* conf
An analytical approach for dynamic range estimation.
DAC
Bin Wu, Jianwen Zhu, Farid N. Najm
2004 A conf
Dynamic range estimation for nonlinear systems.
ICCAD
Bin Wu, Jianwen Zhu, Farid N. Najm
2004 — conf
Interconnect capacitance estimation for FPGAs.
ASP-DAC
Jason Helge Anderson, Farid N. Najm
2004 A conf
Low-power programmable routing circuitry for FPGAs.
ICCAD
Jason Helge Anderson, Farid N. Najm
2004 J jnl
Power estimation techniques for FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Jason Helge Anderson, Farid N. Najm
2004 A* conf
Statistical timing analysis based on a timing yield model.
DAC
Farid N. Najm, Noel Menezes
2004 A* conf
Worst-case circuit delay taking into account power supply variations.
DAC
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
2003 A* conf
A static pattern-independent technique for power grid voltage integrity verification.
DAC
Dionysios Kouroussis, Farid N. Najm
2003 — conf
Design Techniques for Gate-Leakage Reduction in CMOS Circuits.
ISQED
Rafik S. Guindi, Farid N. Najm
2003 A conf
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files.
ISLPED
Kavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm
2003 J jnl
Energy and peak-current per-cycle estimation at RTL.
IEEE Trans. Very Large Scale Integr. Syst.
Subodh Gupta, Farid N. Najm
2003 J jnl
Low-leakage asymmetric-cell SRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Navid Azizi, Farid N. Najm, Andreas Moshovos
2003 A conf
Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations.
ICCAD
Imad A. Ferzli, Farid N. Najm
2003 A* conf
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations.
DAC
Imad A. Ferzli, Farid N. Najm
2003 — conf
Switching activity analysis and pre-layout activity prediction for FPGAs.
SLIP
Jason Helge Anderson, Farid N. Najm
2003 A conf
Timing Analysis in Presence of Power Supply and Ground Voltage Variations.
ICCAD
Rubil Ahmadi, Farid N. Najm
2002 J jnl
A multigrid-like technique for power grid analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
2002 J jnl
A technique for Improving dual-output domino logic.
IEEE Trans. Very Large Scale Integr. Syst.
Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
2002 J jnl
Estimation of state line statistics in sequential circuits.
ACM Trans. Design Autom. Electr. Syst.
Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
2002 A conf
High-level area estimation.
ISLPED
Kavel M. Büyüksahin, Farid N. Najm
2002 A* conf
High-level current macro-model for power-grid analysis.
DAC
Srinivas Bodapati, Farid N. Najm
2002 A conf
Low-leakage asymmetric-cell SRAM.
ISLPED
Navid Azizi, Andreas Moshovos, Farid N. Najm
2002 — conf
Power-aware technology mapping for LUT-based FPGAs.
FPT
Jason Helge Anderson, Farid N. Najm
2001 — conf
A gate-level timing model for SOI circuits.
ICECS
Mehrdad Shahriari, Farid N. Najm
2001 A conf
Frequency-domain supply current macro-model.
ISLPED
Srinivas Bodapati, Farid N. Najm
2001 — conf
I/O buffer placement methodology for ASICs.
ICECS
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
2001 A conf
Multigrid-Like Technique for Power Grid Analysis.
ICCAD
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
2001 J jnl
Power estimation for large sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Joseph N. Kozhaya, Farid N. Najm
2001 J jnl
Prelayout estimation of individual wire lengths.
IEEE Trans. Very Large Scale Integr. Syst.
Srinivas Bodapati, Farid N. Najm
2000 — conf
A Statistical Model for Electromigration Failures.
ISQED
Gilbert Yoh, Farid N. Najm
2000 J jnl
Analytical models for RTL power estimation of combinational andsequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Subodh Gupta, Farid N. Najm
2000 A conf
High-level power estimation with interconnect effects.
ISLPED
Kavel M. Büyüksahin, Farid N. Najm
2000 J jnl
Power modeling for high-level power estimation.
IEEE Trans. Very Large Scale Integr. Syst.
Subodh Gupta, Farid N. Najm
2000 — conf
Pre-layout estimation of individual wire lengths.
SLIP
Srinivas Bodapati, Farid N. Najm
1999 A conf
An optimization technique for dual-output domino logic.
ISLPED
Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
1999 A conf
Energy-per-cycle estimation at RTL.
ISLPED
Subodh Gupta, Farid N. Najm
1999 J jnl
High-level area and power estimation for VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mahadevamurty Nemani, Farid N. Najm
1999 A conf
Power macro-models for DSP blocks with application to high-level synthesis.
ISLPED
Subodh Gupta, Farid N. Najm
1999 A ed.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999
ISLPED
Farid N. Najm, Jason Cong, David T. Blaauw
1998 A* conf
Delay Estimation VLSI Circuits from a High-Level View.
DAC
Mahadevamurty Nemani, Farid N. Najm
1998 J jnl
Guest Editorial.
VLSI Design
Farid N. Najm, Gary Yeap
1998 J jnl
Post-Mapping Transformations for Low-Power Synthesis.
VLSI Design
Rajendran Panda, Farid N. Najm
1998 J jnl
Statistical Estimation of the , Switching Activity in VLSI Circuits.
VLSI Design
Farid N. Najm, Michael G. Xakellis
1997 A conf
Accurate power estimation for large sequential circuits.
ICCAD
Joseph N. Kozhaya, Farid N. Najm
1997 A conf
High-level area and power estimation for VLSI circuits.
ICCAD
Mahadevamurty Nemani, Farid N. Najm
1997 — conf
Monte-Carlo approach for power estimation in sequential circuits.
ED&TC
Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
1997 A* conf
Power Macromodeling for High Level Power Estimation.
DAC
Subodh Gupta, Farid N. Najm
1997 A* conf
Technology-Dependent Transformations for Low-Power Synthesis.
DAC
Rajendran Panda, Farid N. Najm
1996 A conf
High-level power estimation and the area complexity of Boolean functions.
ISLPED
Mahadevamurty Nemani, Farid N. Najm
1996 J jnl
Towards a high-level power estimation capability [digital ICs].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mahadevamurty Nemani, Farid N. Najm
1995 A* conf
Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits.
DAC
Farid N. Najm, Michael Y. Zhang
1995 A* conf
Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits.
DAC
Farid N. Najm
1995 J jnl
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
1995 A* conf
Power Estimation in Sequential Circuits.
DAC
Farid N. Najm, Shashank Goel, Ibrahim N. Hajj
1995 A conf
Power estimation techniques for integrated circuits.
ICCAD
Farid N. Najm
1995 — conf
Towards a high-level power estimation capability.
ISLPD
Farid N. Najm
1994 J jnl
A survey of power estimation techniques in VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Farid N. Najm
1994 C conf
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits.
ISCAS
Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
1994 J jnl
Low-pass filter for computing the transition density in digital circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farid N. Najm
1994 A* conf
Statistical Estimation of the Switching Activity in Digital Circuits.
DAC
Michael G. Xakellis, Farid N. Najm
1993 J jnl
A Monte Carlo approach for power estimation.
IEEE Trans. Very Large Scale Integr. Syst.
Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick
1993 A* conf
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits.
DAC
Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj
1993 J jnl
Transition density: a new measure of activity in digital circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farid N. Najm
1992 A* conf
Maximum Current Estimation in CMOS Circuits.
DAC
Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
1992 A conf
McPOWER: a Monte Carlo approach to power estimation.
ICCAD
Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick
1991 J jnl
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farid N. Najm, Ibrahim N. Hajj, Ping Yang
1991 A* conf
Transition Density, A Stochastic Measure of Activity in Digital Circuits.
DAC
Farid N. Najm
1990 J jnl
Probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj
1990 J jnl
The complexity of fault detection in MOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farid N. Najm, Ibrahim N. Hajj
1989 A conf
Computation of bus current variance for reliability estimation of VLSI circuits.
ICCAD
Farid N. Najm, Ibrahim N. Hajj, Ping Yang
1989 C conf
Electromigration median time-to-failure based on a stochastic current waveform.
ICCD
Farid N. Najm, Ibrahim N. Hajj, Ping Yang
1989 — —
Probabilistic simulation for reliability analysis of VLSI circuits
Farid N. Najm
1988 A conf
CREST-a current estimator for CMOS circuits.
ICCAD
Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj
1988 A* conf
Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits.
DAC
Richard Burch, Farid N. Najm, Ping Yang, Dale E. Hocevar