Fareena Saqib

39 papers A 2B 1C 2Journal 17Unranked 17
YearRankTypeTitle / Venue / Authors
2024 J jnl
AutoDetect: Novel Autoencoding Architecture for Counterfeit IC Detection.
J. Hardw. Syst. Secur.
Chaitanya Bhure, Geraldine Shirley Nicholas, Shajib Ghosh, Navid Asadi, Fareena Saqib
2023 J jnl
Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V.
CoRR
Geraldine Shirley Nicholas, Dhruvakumar Vikas Aklekar, Bhavin Thakar, Fareena Saqib
2023 J jnl
Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V.
Cryptogr.
Geraldine Shirley Nicholas, Dhruvakumar Vikas Aklekar, Bhavin Thakar, Fareena Saqib
2022 — conf
Dynamic Key Updates for LUT Locked Design.
HOST
Jakub Slowik, Gregory Williams, Rummah Albashir, Anthony Samagio, Geraldine Shirley Nicholas, Fareena Saqib
2021 J jnl
A Delay-Based Machine Learning Model for DMA Attack Mitigation.
Cryptogr.
Yutian Gui, Chaitanya Bhure, Marcus Hughes, Fareena Saqib
2021 — conf
A Lightweight Delay-based Authentication Scheme for DMA Attack Mitigation.
ISQED
Yutian Gui, Ali Shuja Siddiqui, Geraldine Shirley Nicholas, Marcus Hughes, Fareena Saqib
2021 J jnl
A Secure Boot Framework with Multi-security Features and Logic-Locking Applications for Reconfigurable Logic.
J. Hardw. Syst. Secur.
Geraldine Shirley Nicholas, Ali Shuja Siddiqui, Sam Reji Joseph, Gregory Williams, Fareena Saqib
2021 — conf
A SoC Design of TrustZone based Key Provisioning for FPGA IP Protection.
MWSCAS
Gregory Williams, Jerry Aizprua, Mohammad Alhaddad, Doua Yang, Nabila BouSaba, Fareena Saqib
2021 — conf
Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V.
ACM Great Lakes Symposium on VLSI
Geraldine Shirley Nicholas, Bhavin Thakar, Fareena Saqib
2020 — conf
A Survey and Analysis on SoC Platform Security in ARM, Intel and RISC-V Architecture.
MWSCAS
Geraldine Shirley Nicholas, Yutian Gui, Fareena Saqib
2020 J jnl
Key Update Countermeasure for Correlation-Based Side-Channel Attacks.
J. Hardw. Syst. Secur.
Yutian Gui, Suyash Mohan Tamore, Ali Shuja Siddiqui, Fareena Saqib
2020 J jnl
Secure Boot for Reconfigurable Architectures.
Cryptogr.
Ali Shuja Siddiqui, Yutian Gui, Fareena Saqib
2020 J jnl
Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity.
Cryptogr.
Ivan Bow, Nahome Bete, Fareena Saqib, Wenjie Che, Chintan Patel, Ryan W. Robucci, Calvin Chan, Jim Plusquellic
2019 — conf
Blockchain Based Distributed Key Provisioning and Secure Communication over CAN FD.
ISVLSI
Bryson Shannon, Spandana Etikala, Yutian Gui, Ali Shuja Siddiqui, Fareena Saqib
2019 — conf
Multilayer Camouflaged Secure Boot for SoCs.
MTV
Ali Shuja Siddiqui, Geraldine Shirley, Sam Reji Joseph, Yutian Gui, Jim Plusquellic, Marten van Dijk, Fareena Saqib
2019 J jnl
Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash).
Cryptogr.
Jeff Calhoun, Cyrus Minwalla, Charles Helmich, Fareena Saqib, Wenjie Che, Jim Plusquellic
2019 — conf
Secure Design Flow of FPGA Based RISC-V Implementation.
IVSW
Ali Shuja Siddiqui, Geraldine Shirley, Shreya Bendre, Girija Bhagwat, Jim Plusquellic, Fareena Saqib
2019 C conf
Security Vulnerabilities of Smart Meters in Smart Grid.
IECON
Yutian Gui, Ali Shuja Siddiqui, Suyash Mohan Tamore, Fareena Saqib
2018 J jnl
An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays.
Cryptogr.
Don Owen Jr., Derek Heeger, Calvin Chan, Wenjie Che, Fareena Saqib, Matthew Areno, Jim Plusquellic
2018 — conf
Delay model and machine learning exploration of a hardware-embedded delay PUF.
HOST
Wenjie Che, Manel Martínez-Ramón, Fareena Saqib, Jim Plusquellic
2018 C conf
Hardware Assisted Security Architecture for Smart Grid.
IECON
Ali Shuja Siddiqui, Yutian Gui, David Lawrence, Stuart Laval, Jim Plusquellic, Madhav D. Manjrekar, Badrul H. Chowdhury, Fareena Saqib
2018 J jnl
Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF.
IEEE Trans. Very Large Scale Integr. Syst.
Wenjie Che, Fareena Saqib, Jim Plusquellic
2018 — conf
Self-authenticating secure boot for FPGAs.
HOST
Goutham Pocklassery, Wenjie Che, Fareena Saqib, Matthew Areno, Jim Plusquellic
2017 J jnl
A Privacy-Preserving, Mutual PUF-Based Authentication Protocol.
Cryptogr.
Wenjie Che, Mitchell T. Martin, Goutham Pocklassery, Venkata K. Kajuluri, Fareena Saqib, Jim Plusquellic
2017 — conf
A novel offset method for improving bitstring quality of a Hardware-Embedded delay PUF.
HOST
Wenjie Che, Jim Plusquellic, Fareena Saqib
2017 J jnl
Analysis of Entropy in a Hardware-Embedded Delay PUF.
Cryptogr.
Wenjie Che, Venkata K. Kajuluri, Mitchell T. Martin, Fareena Saqib, Jim Plusquellic
2017 — conf
Hardware based protection against malwares by PUF based access control mechanism.
MWSCAS
Ali Shuja Siddiqui, Chia-Che Lee, Fareena Saqib
2017 J jnl
Leveraging Distributions in Physical Unclonable Functions.
Cryptogr.
Wenjie Che, Venkata K. Kajuluri, Fareena Saqib, Jim Plusquellic
2017 — conf
Physical unclonable functions and dynamic partial reconfiguration for security in resource-constrained embedded systems.
HOST
Goutham Pocklassery, Venkata K. Kajuruli, James F. Plusquellic, Fareena Saqib
2017 — conf
Secure communication over CANBus.
MWSCAS
Ali Shuja Siddiqui, Yutian Gui, Jim Plusquellic, Fareena Saqib
2017 — conf
Secure intra-vehicular communication over CANFD.
AsianHOST
Ali Shuja Siddiqui, Chia-Che Lee, Wenjie Che, Jim Plusquellic, Fareena Saqib
2016 A conf
On detecting delay anomalies introduced by hardware trojans.
ICCAD
Dylan Ismari, Jim Plusquellic, Charles Lamech, Swarup Bhunia, Fareena Saqib
2016 — conf
Poster: Hardware based security enhanced framework for automotives.
VNC
Ali Shuja Siddiqui, Yutian Gui, Jim Plusquellic, Fareena Saqib
2015 B conf
Cyber-physical systems: A security perspective.
ETS
Charalambos Konstantinou, Michail Maniatakos, Fareena Saqib, Shiyan Hu, Jim Plusquellic, Yier Jin
2015 — conf
GDS-II Trojan detection using multiple supply pad VDD and GND IDDQs in ASIC functional units.
HOST
Ian Wilcox, Fareena Saqib, James F. Plusquellic
2015 A conf
PUF-Based Authentication.
ICCAD
Wenjie Che, Fareena Saqib, Jim Plusquellic
2015 J jnl
Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF).
IEEE Trans. Computers
Fareena Saqib, Aindrik Dutta, Jim Plusquellic, Philip Ortiz, Marios S. Pattichis
2015 J jnl
Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL.
IEEE Trans. Very Large Scale Integr. Syst.
Fareena Saqib, Dylan Ismari, Charles Lamech, Jim Plusquellic
2014 J jnl
ASIC implementation of a hardware-embedded physical unclonable function.
IET Comput. Digit. Tech.
Fareena Saqib, Matthew Areno, Jim Aarestad, James F. Plusquellic