Fangxu Lv - RankMe

40 papers Journal 20Unranked 20

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 61.4 Gb/s/mm Wireline Transceiver Using a 7 bit-Over-8 Lane Symmetric Correlated Coding for High-Density Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. Mingche Lai, Geng Zhang, Fangxu Lv, Liquan Xiao, Xuqiang Zheng, Heng Huang, Kewei Xin, Liangyong Yuan, Ruixiao Kuai, Bolin Ren, Ruotian Yin, Guohe Zhang, Chao Fan
2026	J	`jnl`	A high speed and reflection cancel adaptive equalization using 4-tap floating FFE and 2-tap speculative pre-decision and loop-refactored DFE for wireline receiver. Microelectron. J. Xiaoyue Hu, Fangxu Lv, Jin Zhang, Jiaqing Xu, Qiang Wang, Cewen Liu, Chaolong Xu, Zhouhao Yang, Jinwen Li
2025	J	`jnl`	A 100 Gb/s PAM4 receiver analog front-end with 33.1-dB boost in 28-nm CMOS process. IEICE Electron. Express Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Wenxiang Zhen, Mingche Lai, Zhi Jin, Xinyu Liu
2025	J	`jnl`	A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS. IEEE J. Solid State Circuits Hua Xu, Mingche Lai, Xuqiang Zheng, Zedong Wang, Jiang Xu, Sai Li, Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo, Xinhua Wang, Zhi Jin, Xinyu Liu
2025	J	`jnl`	A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment. IEEE J. Solid State Circuits Zedong Wang, Xuqiang Zheng, Yu He, Hua Xu, Sai Li, Zunsong Yang, Fangxu Lv, Mingche Lai, Xinyu Liu
2025	J	`jnl`	A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers. IEEE Trans. Very Large Scale Integr. Syst. Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang
2025	J	`jnl`	A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver. Microelectron. J. Cewen Liu, Xingyun Qi, Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai
2025	J	`jnl`	An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. Mingche Lai, Chaolong Xu, Fangxu Lv, Jiaqing Xu, Qiang Wang, Yang Ou, Xiaoyue Hu, Cewen Liu, Zhouhao Yang
2025	—	`conf`	Real-Time Demonstration of FPGA-Based Advanced Equalizer with ZF-NL-RSSE for Data Center Interconnects. ECOC Zhouhao Yang, Fangxu Lv, Mingche Lai, Zhang Luo, Weixia Xu, Chaolong Xu, Kefan Ma, Xiaoyue Hu, Cewen Liu, Zheng Peng, Xianchao Zeng
2024	J	`jnl`	A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface. Microelectron. J. Bolin Ren, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu
2024	J	`jnl`	A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. Microelectron. J. Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang
2024	J	`jnl`	A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE. IEICE Electron. Express Xiaoyue Hu, Fangxu Lv, Mingche Lai, Zhang Luo, Qiang Wang, Chaolong Xu, Ruotian Yin, Zhouhao Yang, Cewen Liu
2024	J	`jnl`	A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process. IEICE Electron. Express Wenchen Wang, Fangxu Lv, Zhengbin Pang, Heng Huang, Zhang Luo, Xingyun Qi, Jiaqing Xu, Geng Zhang, Kewei Xin, Chengzhuo Zhao
2024	—	`conf`	A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver. A-SSCC Chaolong Xu, Fangxu Lv, Mingche Lai, Zhang Luo, Xingyun Qi, Jiaqing Xu, Qiang Wang, Liquan Xiao, Cewen Liu, Hua Xu
2024	—	`conf`	An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM. CICC Yu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu
2024	J	`jnl`	Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization. IEEE Trans. Circuits Syst. I Regul. Pap. Zhang Luo, Sichun Du, Zedi Zhang, Fangxu Lv, Qinghui Hong, Mingche Lai
2024	—	`conf`	FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver. ACM Great Lakes Symposium on VLSI Chaolong Xu, Fangxu Lv, Zhengbin Pang, Liquan Xiao, Zhouhao Yang
2024	J	`jnl`	Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li
2023	J	`jnl`	A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology. Microelectron. J. Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Zhaoyang Liu, Hua Xu, Weijie Li, Zhi Jin, Mingche Lai, Xinyu Liu
2023	—	`conf`	A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks. HPCC/DSS/SmartCity/DependSys Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu
2023	—	`conf`	Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications. ICCEIC Qing Liu, Heming Wang, Fangxu Lv, Geng Zhang, Dongbin Lv
2022	J	`jnl`	A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi
2021	—	`conf`	A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface. ASICON Geng Zhang, Fangxu Lv, Zhengbin Pang, Heming Wang, Dongbin Lv, Tao Liu, Jinwang Zhang
2021	—	`conf`	An Adaptive Equalization Algorithm for High Speed SerDes. ASICON Miaomiao Wu, Zhengbin Pang, Fangxu Lv, Jianjun Shi, Heming Wang, Tao Liu, Dechao Lu, Zheng Wang
2021	—	`conf`	An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits. ASICON Tao Liu, Fangxu Lv, Bin Liang, Heming Wang, Jianye Wang, Miaomiao Wu
2020	—	`conf`	A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology. ACA Zhengbin Pang, Fangxu Lv, Weiping Tang, Mingche Lai, Kaile Guo, Yuxuan Wu, Tao Liu, Miaomiao Wu, Dechao Lu
2020	J	`jnl`	A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. IEEE J. Solid State Circuits Xuqiang Zheng, Hao Ding, Feng Zhao, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
2020	J	`jnl`	Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. IEEE J. Solid State Circuits Xuqiang Zheng, Fangxu Lv, Lei Zhou, DanYu Wu, Jin Wu, Chun Zhang, Woogeun Rhee, Xinyu Liu
2019	—	`conf`	A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. ESSCIRC Hao Ding, Xuqiang Zheng, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
2019	—	`conf`	A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology. MWSCAS Dengjie Wang, Hong Chen, Wenhuan Luan, Xin Lin, Fangxu Lv, Ziqiang Wang, Hanjun Jiang, Chun Zhang, Zhihua Wang
2018	J	`jnl`	A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. Microelectron. J. Fangxu Lv, Xuqiang Zheng, Feng Zhao, Jianye Wang, Shigang Yue, Ziqiang Wang, Weidong Cao, Yajun He, Chun Zhang, Hanjun Jiang, Zhihua Wang
2017	—	`conf`	A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. CICC Xuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
2017	—	`conf`	A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. CICC Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
2017	—	`conf`	A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology. MWSCAS Fangxu Lv, Xuqiang Zheng, Shuai Yuan, Ziqiang Wang, Yajun He, Chun Zhang, Zhihua Wang, Jianye Wang
2017	J	`jnl`	A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. IEEE J. Solid State Circuits Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shuai Yuan, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang, Hanjun Jiang
2017	—	`conf`	An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes. MWSCAS Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, Shuai Yuan, Chun Zhang, Zhihua Wang, Hanjun Jiang
2017	—	`conf`	Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology. ASICON Fangxu Lv, Jianye Wang, Dengjie Wang, Yongcong Liu, Ziqiang Wang
2016	—	`conf`	A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. ESSCIRC Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
2015	—	`conf`	A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. ASICON Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li
2014	—	`conf`	Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network. CWSN Yu Wang, Jincheng Zhang, Quan Wang, Fangxu Lv, Kewei Chen