Fakhreddine Ghaffari

59 papers B 1C 12Journal 14Unranked 32

Year	Rank	Type	Title / Venue / Authors
2026	C	`conf`	A Robust Motor Imagery EEG Classification Framework Using Adaptive Channel-Window Selection and Temporal Feature Pooling. ICCE Marwan Hilali, Kais Belwafi, Fakhreddine Ghaffari
2025	—	`conf`	Characterization-Guided Strategies for Transients Faults Mitigation in Digitals Circuits. ICECS Maxime Le Bigot, François Leroy, Fakhreddine Ghaffari, Olivier Romain
2025	—	`conf`	Systematic Framework Leveraging Early Assessment of DNN Reliability for Efficient and Reliable FPGA-Based Inference Deployment. ICECS Nguyen Trinh Vu Dang, Otmane Aït Mohamed, Fakhreddine Ghaffari
2024	—	`conf`	Enhancing Deep Learning-Based Epileptic Seizure Detection with Generative AI Techniques. ICM Hamza Bouallagui, Hamza Chniter, Fakhreddine Ghaffari, Olivier Romain
2024	J	`jnl`	User Evaluation of a Shared Robot Control System Combining BCI and Eye Tracking in a Portable Augmented Reality User Interface. Sensors Arnau Dillen, Mohsen Omidi, Fakhreddine Ghaffari, Olivier Romain, Bram Vanderborght, Bart Roelands, Ann Nowé, Kevin De Pauw
2023	—	`conf`	Layout-based reliability analysis of openMSP430 register file under external radiations. ICM Vivek Bansal, Otmane Aït Mohamed, Fakhreddine Ghaffari
2023	—	`conf`	Optimal Sensor Set for Decoding Motor Imagery from EEG. NER Arnau Dillen, Fakhreddine Ghaffari, Olivier Romain, Bram Vanderborght, Romain Meeusen, Bart Roelands, Kevin De Pauw
2023	J	`jnl`	The Syndrome Bit Flipping Algorithm for LDPC Codes. IEEE Commun. Lett. Emmanuel Boutillon, Chris Winstead, Fakhreddine Ghaffari
2021	—	`conf`	An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders. ICECS Fakhreddine Ghaffari, Khoa Le
2021	J	`jnl`	Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Hangxuan Cui, Fakhreddine Ghaffari, Khoa Le, David Declercq, Jun Lin, Zhongfeng Wang
2021	—	`conf`	FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. DFT Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid, Philippe Roche, Fakhreddine Ghaffari, Olivier Romain
2021	—	`conf`	Reduced Complexity of a Successive Cancellation Based Decoder for NB-Polar Codes. ISTC F. Cochachin, Laura Luzzi, Fakhreddine Ghaffari
2019	—	`conf`	A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes. ISCIT Hangxuan Cui, Khoa Le, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Emmanuel Boutillon, Chris Winstead, Bane Vasic
2019	C	`conf`	An Adaptation of Min-Sum Decoder for 5G Low-Density Parity-Check Codes. ISCAS Khoa LeTrung, Fakhreddine Ghaffari, David Declercq
2019	C	`conf`	An Enhanced Offset Min-Sum decoder for 5G LDPC Codes. APCC Hangxuan Cui, Khoa LeTrung, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang
2019	—	`conf`	Performance Enhancement of Polar Codes in Multi-level Cell NAND Flash Memories using Systematic Encoding. ISCIT Duc-Phuc Nguyen, Khoa Le, Fakhreddine Ghaffari, David Declercq
2019	C	`conf`	Reliability Enhancement for Multi-level Cell NAND Flash Memory Using Error Asymmetry. APCC Duc-Phuc Nguyen, Khoa LeTrung, Fakhreddine Ghaffari, David Declercq
2019	—	`conf`	The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes. NEWCAS Fakhreddine Ghaffari, Khoa Le, David Declercq
2018	J	`jnl`	An Imprecise Stopping Criterion Based on In-Between Layers Partial Syndromes. IEEE Commun. Lett. David Declercq, Valentin Savin, Oana Boncalo, Fakhreddine Ghaffari
2018	J	`jnl`	Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders. IEEE Trans. Very Large Scale Integr. Syst. Thien Truong Nguyen-Ly, Valentin Savin, Khoa Le, David Declercq, Fakhreddine Ghaffari, Oana Boncalo
2018	J	`jnl`	Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. Burak Unal, Ali Akoglu, Fakhreddine Ghaffari, Bane Vasic
2018	C	`conf`	Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. ISCAS Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin, Oana Boncalo
2018	—	`conf`	On the Use of Hard-Decision LDPC Decoders on MLC NAND Flash Memory. SSD Khoa Le, Fakhreddine Ghaffari
2018	—	`conf`	On the use of Probabilistic Parallel Bit-Flipping decoder for the storage systems. MWSCAS Khoa Le, Fakhreddine Ghaffari, David Declercq
2018	C	`conf`	Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels. ISCAS Fakhreddine Ghaffari, Bane Vasic
2018	—	`conf`	Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders. ISTC Chris Winstead, Tasnuva Tithi, Emmanuel Boutillon, Fakhreddine Ghaffari
2018	—	`conf`	The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes. MWSCAS Khoa Le, Fakhreddine Ghaffari, David Declercq
2018	J	`jnl`	Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Khoa Le, David Declercq, Fakhreddine Ghaffari, Lounis Kessal, Oana Boncalo, Valentin Savin
2017	J	`jnl`	A Hardware/Software Prototype of EEG-based BCI System for Home Device Control. J. Signal Process. Syst. Kais Belwafi, Fakhreddine Ghaffari, Ridha Djemal, Olivier Romain
2017	J	`jnl`	Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders. CoRR Thien Truong Nguyen-Ly, Valentin Savin, Khoa Le, David Declercq, Fakhreddine Ghaffari, Oana Boncalo
2017	—	`conf`	Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder. NEWCAS Burak Unal, Fakhreddine Ghaffari, Ali Akoglu, David Declercq, Bane Vasic
2017	—	`conf`	Efficient FPGA implementation of probabilistic gallager B LDPC decoder. ICECS Fakhreddine Ghaffari, Burak Unal, Ali Akoglu, Khoa Le, David Declercq, Bane Vasic
2017	J	`jnl`	Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping. IEEE Trans. Circuits Syst. I Regul. Pap. Khoa Le, Fakhreddine Ghaffari, David Declercq, Bane Vasic
2017	—	`conf`	Error rate estimation of a design implemented in an FPGA based on the operating conditions. EWDTS Marc Alexandre Kacou, Fakhreddine Ghaffari, Olivier Romain, Bruno Condamin
2017	C	`conf`	FPGA static timing analysis enhancement based on real operating conditions. IECON Marc Alexandre Kacou, Fakhreddine Ghaffari, Olivier Romain, Bruno Condamin
2017	C	`conf`	Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders. ISCAS Khoa Le, Fakhreddine Ghaffari, David Declercq, Bane Vasic
2017	B	`conf`	Multi-Mode Low-Latency Software-Defined Error Correction for Data Centers. ICCCN Fakhreddine Ghaffari, Ali Akoglu, Bane Vasic, David Declercq
2017	—	`conf`	Probabilistic model of AFDX frames reception for end system backlog assessment. SIES Yohan Baga, Morgane Richaud, Fakhreddine Ghaffari, Etienne Zante, David Declercq, Michael Nahmiyace
2016	C	`conf`	Influence of high-power electric motor on an FPGA used in the drive system of electric car. IECON Marc Alexandre Kacou, Fakhreddine Ghaffari, Olivier Romain, Bruno Condamin
2016	—	`conf`	Noise-aided gradient descent bit-flipping decoders approaching maximum likelihood decoding. ISTC David Declercq, Chris Winstead, Bane Vasic, Fakhreddine Ghaffari, Predrag Ivanis, Emmanuel Boutillon
2016	—	`conf`	Non-surjective finite alphabet iterative decoders. ICC Thien Truong Nguyen-Ly, Khoa Le, Valentin Savin, David Declercq, Fakhreddine Ghaffari, Oana Boncalo
2016	—	`conf`	Online Adaptive Filters to Classify Left and Right Hand Motor Imagery. BIOSIGNALS Kais Belwafi, Ridha Djemal, Fakhreddine Ghaffari, Olivier Romain, Bouraoui Ouni, Sofien Gannouni
2015	—	`conf`	Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders. MIXDES Andrei Hera, Oana Boncalo, Constantina-Elena Gavriliu, Alexandru Amaricai, Valentin Savin, David Declercq, Fakhreddine Ghaffari
2015	C	`conf`	Efficient realization of probabilistic gradient descent bit flipping decoders. ISCAS Khoa Le, David Declercq, Fakhreddine Ghaffari, Christian Spagnol, Emanuel M. Popovici, Predrag Ivanis, Bane Vasic
2015	—	`conf`	FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding. NEWCAS Truong Nguyen-Ly, Khoa Le, Fakhreddine Ghaffari, Alexandru Amaricai, Oana Boncalo, Valentin Savin, David Declercq
2014	—	`conf`	An embedded implementation of home devices control system based on brain computer interface. ICM Kais Belwafi, Fakhreddine Ghaffari, Olivier Romain, Ridha Djemal
2014	—	`conf`	Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overhead. ReConFig Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado
2014	—	`conf`	Fast SRAM-FPGA fault injection platform based on dynamic partial reconfiguration. ICM Fakhreddine Ghaffari, Fouad Sahraoui, Mohamed El Amine Benkhelifa, Bertrand Granado, Marc Alexandre Kacou, Olivier Romain
2014	—	`conf`	Reliability assessment of backward error recovery for SRAM-based FPGAs. IDT Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado
2013	—	`conf`	An efficient BER-based reliability method for SRAM-based FPGA. IDT Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado
2011	J	`jnl`	Dynamic Application Model for Scheduling with Uncertainty on Reconfigurable Architectures. Int. J. Reconfigurable Comput. Ismail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid
2010	—	`conf`	Novel Approach for Modeling Very Dynamic and Flexible Real Time Applications. ReCoSoC Ismail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid
2010	—	`conf`	Prediction performance method for dynamic task scheduling, case study: the OLLAF Architecture. IDT Ismail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid
2009	J	`jnl`	Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures. EURASIP J. Embed. Syst. Fakhreddine Ghaffari, Benoît Miramond, François Verdier
2008	C	`conf`	Dynamic Adaptation of Hardware-Software Scheduling for Reconfigurable System-on-Chip. IEEE International Workshop on Rapid System Prototyping Fakhreddine Ghaffari, Benoît Miramond, François Verdier
2007	J	`jnl`	Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures. Trans. High Perform. Embed. Archit. Compil. Fakhreddine Ghaffari, Michel Auguin, Mohamed Abid, Maher Ben Jemaa
2006	—	`conf`	An efficient on-line Approach for on-chip HW/SW partitioner and scheduler. ARCS Workshops Fakhreddine Ghaffari, Michel Auguin
2005	C	`conf`	An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems. DSD Fakhreddine Ghaffari, Michel Auguin, Mohamed Abid, Maher Benjemaa