Fahim ur Rahman

13 papers Journal 4Unranked 9
YearRankTypeTitle / Venue / Authors
2023 — conf
Multiple Skin-Disease Classification Based on Machine Vision Using Transfer Learning Approach.
ICCCNT
Md Abrar Hamim, Shahadat Hossain Sajim, Fahim ur Rahman, F. M. Tanmoy
2023 — conf
Performance Evaluation of Several Transfer Learning Models for Classification of Road Surface State.
ICCIDS
Fahim ur Rahman, Md. Tanvir Ahmed, Emran Khan, Md Mahfuzur Rahman, Shafin Ahamed, Shahriar Mamun, Md. Mehedi Hasan
2023 — conf
Predicting User Perception Regarding Usefulness of Google Classroom Through Machine Learning Algorithms.
ICCCNT
Emran Khan, Afroza Akter, Sabrina Sultana Prity, Fahim ur Rahman
2022 — conf
A Comparative Study of Different Transfer Learning Models for Classification of Urban Manhole States.
ICCTA
Md. Tanvir Ahmed, Md Risfat Amin, Fahim ur Rahman, Mahedi Hasan Abeer, Nusrat Nabi, Md. Sazzadur Ahamed
2022 — conf
A Comparative Study on Road Surface State Assessment Using Transfer Learning Approach.
ICCCNT
Fahim ur Rahman, Md. Tanvir Ahmed, Md Risfat Amin, Nusrat Nabi, Md. Sazzadur Ahamed
2020 J jnl
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS.
IEEE J. Solid State Circuits
Fahim ur Rahman, Rajesh Pamula, Visvesh S. Sathe
2019 J jnl
A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation.
IEEE J. Solid State Circuits
Fahim ur Rahman, Greg Taylor, Visvesh Sathe
2019 J jnl
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains.
IEEE J. Solid State Circuits
Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
2019 J jnl
An All-Digital Fused PLL-Buck Architecture for 82% Average V
IEEE J. Solid State Circuits
Xun Sun, Fahim ur Rahman, Venkata Rajesh Pamula, Sung Kim, Xi Li, Naveen John, Visvesh S. Sathe
2019 — conf
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS.
ISSCC
Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe
2018 — conf
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor.
ISSCC
Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe
2018 — conf
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS.
VLSI Circuits
Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe
2018 — conf
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor.
VLSI Circuits
Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe