Fahad Bin Muslim

16 papers Misc 1Journal 11Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
SAPER-AI accelerator: a systolic array-based power-efficient reconfigurable AI accelerator.
Frontiers Inf. Technol. Electron. Eng.
Fahad Bin Muslim, Kashif Inayat, Muhammad Zain Siddiqi, Safiullah Khan, Tayyeb Mahmood, Ihtesham Ul Islam
2024 J jnl
FPGA-assisted Design Space Exploration of Parameterized AI Accelerators: A Quickloop Approach.
J. Syst. Archit.
Kashif Inayat, Fahad Bin Muslim, Tayyeb Mahmood, Jaeyong Chung
2024 J jnl
LPCHISEL: Automatic power intent generation for a chisel-based ASIC design.
Comput. Electr. Eng.
Fahad Bin Muslim, Kashif Inayat, Safiullah Khan
2024 J jnl
Securing the IoT ecosystem: ASIC-based hardware realization of Ascon lightweight cipher.
Int. J. Inf. Sec.
Safiullah Khan, Kashif Inayat, Fahad Bin Muslim, Yasir Ali Shah, Muhammad Atif Ur Rehman, Ayesha Khalid, Malik Imran, Akmalbek Abdusalomov
2023 J jnl
Power-Intent Systolic Array Using Modified Parallel Multiplier for Machine Learning Acceleration.
Sensors
Kashif Inayat, Fahad Bin Muslim, Javed Iqbal, Syed Agha Hassnain Mohsan, Hend Khalid Alkahtani, Samih Mohemmed Mostafa
2020 J jnl
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Ali Zahir, Shadan Khan Khattak, Anees Ullah, Pedro Reviriego, Fahad Bin Muslim, Waleed Ahmad
2020 J jnl
Implementation of Symbol Timing Recovery for Estimation of Clock Skew.
CoRR
S. M. Usman Hashmi, Muntazir Hussain, Fahad Bin Muslim, Kashif Inayat, Seong Oun Hwang
2020 J jnl
Simulations and experimental validation of one cycle controlled nine-level inverter using FPGA.
Comput. Electr. Eng.
Azhar Ul-Haq, Marium Jalal, Muhammad Aamir, Carlo Cecati, Fahad Bin Muslim, Arsalan Ahmad Raja, Javed Iqbal
2017 J jnl
Efficient FPGA Implementation of OpenCL High-Performance Computing Applications via High-Level Synthesis.
IEEE Access
Fahad Bin Muslim, Liang Ma, Mehdi Roozmeh, Luciano Lavagno
2017 — —
Energy-efficient hardware design based on high-level synthesis.
Fahad Bin Muslim
2017 J jnl
High-Level Synthesis for Semi-Global Matching: Is the Juice Worth the Squeeze?
IEEE Access
Affaq Qamar, Fahad Bin Muslim, Francesco Gregoretti, Luciano Lavagno, Mihai Teodor Lazarescu
2017 J jnl
LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow.
Microprocess. Microsystems
Affaq Qamar, Fahad Bin Muslim, Javed Iqbal, Luciano Lavagno
2016 — conf
Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL.
FedCSIS (Position Papers)
Fahad Bin Muslim, Alexandros Demian, Liang Ma, Luciano Lavagno, Affaq Qamar
2016 — conf
High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and Synthesis.
EMS
Liang Ma, Fahad Bin Muslim, Luciano Lavagno
2015 — conf
Analysis and Implementation of the Semi-Global Matching 3D Vision Algorithm Using Code Transformations and High-Level Synthesis.
VTC Spring
Affaq Qamar, Fahad Bin Muslim, Luciano Lavagno
2015 Misc conf
Low power methodology for an ASIC design flow based on high-level synthesis.
SoftCOM
Fahad Bin Muslim, Affaq Qamar, Luciano Lavagno