Fabio Padovan

20 papers Journal 10Unranked 10
YearRankTypeTitle / Venue / Authors
2026 J jnl
Design of a Tank-Optimized 20 GHz VCO With Fourth Harmonic Extraction Achieving 193.8 dBc/Hz Peak FoM in 22 nm FDSOI.
IEEE Trans. Circuits Syst. II Express Briefs
Sarah Koop-Brinkmann, Victor Lasserre, Adilet Dossanov, Fabio Padovan, Andrea Mazzanti, Vadim Issakov
2024 J jnl
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs.
IEEE J. Solid State Circuits
Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
2023 J jnl
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Davide Manente, Fabio Quadrelli, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
2022 J jnl
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise.
IEEE J. Solid State Circuits
Lorenzo Tomasin, Pietro Andreani, Giovanni Boi, Fabio Padovan, Andrea Bevilacqua
2022 — conf
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS.
ESSCIRC
Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
2022 J jnl
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications.
IEEE J. Solid State Circuits
Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
2021 — conf
A 22-31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS.
ESSCIRC
Davide Manente, Fabio Quadrelli, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
2020 J jnl
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects.
IEEE J. Solid State Circuits
Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
2019 — conf
A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion.
ESSCIRC
Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Roberto Nonis, Andrea Bevilacqua
2019 — conf
A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS.
ESSCIRC
Matteo Bassi, Giovanni Boi, Fabio Padovan, Jonas Fritzin, Stefano Di Martino, Daniel Knauder, Andrea Bevilacqua
2018 — conf
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations.
ISSCC
Fabio Padovan, Fabio Quadrelli, Matteo Bassi, Marc Tiebout, Andrea Bevilacqua
2018 J jnl
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs
Alessandro Franceschin, Fabio Padovan, Roberto Nonis, Andrea Bevilacqua
2017 — conf
A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset.
ESSCIRC
Fabio Boscolo, Fabio Padovan, Fabio Quadrelli, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
2016 J jnl
A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation.
IEEE J. Solid State Circuits
Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
2016 — conf
A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers.
ESSCIRC
Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
2016 J jnl
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Stefano Brenna, Fabio Padovan, Andrea Neviani, Andrea Bevilacqua, Andrea Bonfanti, Andrea L. Lacaita
2015 — conf
A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation.
ESSCIRC
Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
2015 J jnl
Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani
2014 — conf
A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS.
ESSCIRC
Fabio Padovan, Andrea Bevilacqua, Andrea Neviani
2012 — conf
A SiGe bipolar VCO for backhaul E-band communication systems.
ESSCIRC
Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani