Fabio Frustaci

65 papers B 1C 6Journal 39Unranked 19

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Leveraging Highly Approximated Multipliers in DNN Inference. IEEE Access Georgios Zervakis, Fabio Frustaci, Ourania Spantidi, Iraklis Anagnostopoulos, Hussam Amrouch, Jörg Henkel
2025	—	`conf`	Robust Human Activity Prediction Through Multi-View Sensor Data Integration. ICHMS Niccolò Petti, Antonio Pellicani, Fabio Frustaci, Francesco Porreca, Gianvito Pio
2025	—	`conf`	Streamlining Serial Communication Protocol Development on SoC Platforms for Code Reusability. ICHMS Francesco Porreca, Raffaele Gravina, Antonio Pellicani, Niccolò Petti, Fabio Frustaci
2024	J	`jnl`	A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations. IEEE Trans. Circuits Syst. II Express Briefs Fabio Frustaci, Fanny Spagnolo, Pasquale Corsonello, Stefania Perri
2024	J	`jnl`	An explainable embedded neural system for on-board ship detection from optical satellite imagery. Eng. Appl. Artif. Intell. Cosimo Ieracitano, Nadia Mammone, Fanny Spagnolo, Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Francesco Carlo Morabito
2024	J	`jnl`	Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs. J. Supercomput. Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2024	C	`conf`	COCOWEARS: A framework for COntinuum COmputing WEARable Systems. ISM Gianluca Aloi, Fabio Frustaci, Raffaele Gravina, Antonio Guerrieri, Gianvito Pio, Claudio Savaglio
2024	J	`jnl`	Efficient implementation of signed multipliers on FPGAs. Comput. Electr. Eng. Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2024	J	`jnl`	Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. IEEE Trans. Very Large Scale Integr. Syst. Fanny Spagnolo, Stefania Perri, Massimo Vatalaro, Fabio Frustaci, Felice Crupi, Pasquale Corsonello
2024	B	`conf`	KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA. FPL Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2024	J	`jnl`	Leveraging Highly Approximated Multipliers in DNN Inference. CoRR Georgios Zervakis, Fabio Frustaci, Ourania Spantidi, Iraklis Anagnostopoulos, Hussam Amrouch, Jörg Henkel
2023	J	`jnl`	A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers. IEEE Trans. Circuits Syst. II Express Briefs Fabio Frustaci, Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
2023	J	`jnl`	Design of Approximate Bilateral Filters for Image Denoising on FPGAs. IEEE Access Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2023	J	`jnl`	Design of Leading Zero Counters on FPGAs. IEEE Embed. Syst. Lett. Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
2023	J	`jnl`	HW/SW Codesign for Approximation-Aware Binary Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Abhilasha Dave, Fabio Frustaci, Fanny Spagnolo, Mikail Yayla, Jian-Jia Chen, Hussam Amrouch
2023	J	`jnl`	Unlocking Efficiency in BNNs: Global by Local Thresholding for Analog-Based HW Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Mikail Yayla, Fabio Frustaci, Fanny Spagnolo, Jian-Jia Chen, Hussam Amrouch
2022	—	`conf`	An FPGA-Based Hardware Accelerator for the k-Nearest Neighbor Algorithm Implementation in Wearable Embedded Systems. AII Antonio Borelli, Fanny Spagnolo, Raffaele Gravina, Fabio Frustaci
2022	—	`conf`	Designing Low-Power and High-Speed FPGA-Based Binary Decision Tree Hardware Accelerators. AII Roman Huzyuk, Fanny Spagnolo, Fabio Frustaci
2022	J	`jnl`	Multibit Full Comparator Logic in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
2022	J	`jnl`	Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes. Sensors Fabio Frustaci, Fanny Spagnolo, Stefania Perri, Giuseppe Cocorullo, Pasquale Corsonello
2021	J	`jnl`	Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA. IEEE Trans. Circuits Syst. II Express Briefs Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
2020	—	`conf`	A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs. ICECS Fanny Spagnolo, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2020	J	`jnl`	Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation. IEEE Trans. Circuits Syst. Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto
2020	J	`jnl`	Parallel architecture of power-of-two multipliers for FPGAs. IET Circuits Devices Syst. Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
2020	—	`conf`	Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip. MECO Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello
2020	J	`jnl`	Stereo vision architecture for heterogeneous systems-on-chip. J. Real Time Image Process. Stefania Perri, Fabio Frustaci, Fanny Spagnolo, Pasquale Corsonello
2019	J	`jnl`	Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. IEEE Trans. Very Large Scale Integr. Syst. Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto
2019	J	`jnl`	Multimodal background subtraction for high-performance embedded systems. J. Real Time Image Process. Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Lorena-de-los-Angeles Guachi-Guachi, Stefania Perri
2018	—	`conf`	Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems. ICECS Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello
2018	C	`conf`	Design of Real-Time FPGA-based Embedded System for Stereo Vision. ISCAS Stefania Perri, Fabio Frustaci, Fanny Spagnolo, Pasquale Corsonello
2018	—	`conf`	Designing Fast Convolutional Engines for Deep Learning Applications. ICECS Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello
2017	J	`jnl`	Design of Efficient BCD Adders in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2016	J	`jnl`	An efficient hardware-oriented stereo matching algorithm. Microprocess. Microsystems Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2016	J	`jnl`	Approximate SRAMs With Dynamic Energy-Quality Management. IEEE Trans. Very Large Scale Integr. Syst. Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2016	J	`jnl`	Design of efficient QCA multiplexers. Int. J. Circuit Theory Appl. Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2015	—	`conf`	A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS. VLSIC Mahmood Khayatzadeh, Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2015	—	`conf`	Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse. PATMOS Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2015	C	`conf`	Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology. ICCD Pasquale Corsonello, Stefania Perri, Fabio Frustaci
2015	J	`jnl`	Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology. IEEE Trans. Very Large Scale Integr. Syst. Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2015	J	`jnl`	Power supply noise in accurate delay model for the sub-threshold domain. Integr. Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2015	J	`jnl`	SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS. IEEE J. Solid State Circuits Fabio Frustaci, Mahmood Khayatzadeh, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2014	—	`conf`	13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS. ISSCC Fabio Frustaci, Mahmood Khayatzadeh, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2014	—	`conf`	A novel background subtraction method based on color invariants and grayscale levels. ICCST Lorena Guachi, Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2014	J	`jnl`	Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. Int. J. Circuit Theory Appl. Fabio Frustaci, Marco Lanuzza, Stefania Perri, Pasquale Corsonello
2014	J	`jnl`	Designing Dynamic Carry Skip Adders: Analysis and Comparison. Circuits Syst. Signal Process. Raffaele De Rose, Marco Lanuzza, Fabio Frustaci, Sohan Purohit
2014	J	`jnl`	Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. IEEE Trans. Circuits Syst. I Regul. Pap. Pasquale Corsonello, Fabio Frustaci, Marco Lanuzza, Stefania Perri
2012	J	`jnl`	Analytical Delay Model Considering Variability Effects in Subthreshold Domain. IEEE Trans. Circuits Syst. II Express Briefs Fabio Frustaci, Pasquale Corsonello, Stefania Perri
2012	J	`jnl`	Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2012	J	`jnl`	Energy-efficient single-clock-cycle binary comparator. Int. J. Circuit Theory Appl. Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello
2011	—	`conf`	Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers. ECCTD Fabio Frustaci, Pasquale Corsonello, Massimo Alioto
2011	C	`conf`	Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology. ISCAS Fabio Frustaci, Pasquale Corsonello, Massimo Alioto
2011	J	`jnl`	Tapered-Vth Approach for Energy-Efficient CMOS Buffers. IEEE Trans. Circuits Syst. I Regul. Pap. Fabio Frustaci, Massimo Alioto, Pasquale Corsonello
2010	—	`conf`	A Low-Leakage Single-Ended 6T SRAM Cell. ICETET Sohit Solanki, Fabio Frustaci, Pasquale Corsonello
2010	C	`conf`	A new low-power high-speed single-clock-cycle binary comparator. ISCAS Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello
2010	J	`jnl`	Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. ACM Trans. Reconfigurable Technol. Syst. Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2010	—	`conf`	Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2010	—	`conf`	Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2009	—	`conf`	A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder. PATMOS Fabio Frustaci, Marco Lanuzza
2009	—	`conf`	An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. ARC Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2009	J	`jnl`	Designing High-Speed Adders in Power-Constrained Environments. IEEE Trans. Circuits Syst. II Express Briefs Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello
2009	J	`jnl`	Low-power split-path data-driven dynamic logic. IET Circuits Devices Syst. Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello
2008	—	`conf`	A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. PATMOS Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
2008	J	`jnl`	High-performance noise-tolerant circuit techniques for CMOS dynamic logic. IET Circuits Devices Syst. Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
2006	C	`conf`	Leakage energy reduction techniques in deep submicron cache memories: a comparative study. ISCAS Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
2006	J	`jnl`	Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. IEEE Trans. Very Large Scale Integr. Syst. Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo