Fabian Schuiki

34 papers A* 1A 3C 2Journal 20Unranked 7

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. CoRR Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2023	J	`jnl`	Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. IEEE Trans. Parallel Distributed Syst. Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2022	J	`jnl`	An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. IEEE Trans. Computers Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini
2021	—	`conf`	A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range. ESSCIRC Thomas Benz, Luca Bertaccini, Florian Zaruba, Fabian Schuiki, Frank K. Gürkaynak, Luca Benini
2021	A	`conf`	Banshee: A Fast LLVM-Based RISC-V Binary Translator. ICCAD Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini
2021	J	`jnl`	FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing. IEEE Trans. Very Large Scale Integr. Syst. Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini
2021	J	`jnl`	Implementing CNN Layers on the Manticore Cluster-Based Many-Core Architecture. CoRR Andreas Kurth, Fabian Schuiki, Luca Benini
2021	A	`conf`	Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. DATE Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2021	J	`jnl`	Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing. IEEE Micro Florian Zaruba, Fabian Schuiki, Luca Benini
2021	J	`jnl`	Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads. IEEE Trans. Computers Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2021	J	`jnl`	Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. IEEE Trans. Computers Fabian Schuiki, Florian Zaruba, Torsten Hoefler, Luca Benini
2021	—	`—`	Streaming architectures for extreme energy efficiency in high-performance computing. Fabian Schuiki
2020	—	`conf`	A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. Hot Chips Symposium Florian Zaruba, Fabian Schuiki, Luca Benini
2020	J	`jnl`	An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. CoRR Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini
2020	J	`jnl`	Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini
2020	—	`conf`	Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems. CF Matheus A. Cavalcante, Andreas Kurth, Fabian Schuiki, Luca Benini
2020	J	`jnl`	FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing. CoRR Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini
2020	J	`jnl`	Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. CoRR Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2020	J	`jnl`	LLHD: A Multi-level Intermediate Representation for Hardware Description Languages. CoRR Fabian Schuiki, Andreas Kurth, Tobias Grosser, Luca Benini
2020	A*	`conf`	LLHD: a multi-level intermediate representation for hardware description languages. PLDI Fabian Schuiki, Andreas Kurth, Tobias Grosser, Luca Benini
2020	C	`conf`	Live Demonstration: Exploiting Body-Biasing for Static Corner Trimming and Maximum Energy Efficiency Operation in 22nm FDX Technology. ISCAS Alfio Di Mauro, Florian Zaruba, Fabian Schuiki, Stefan Mach, Luca Benini
2020	J	`jnl`	Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. CoRR Florian Zaruba, Fabian Schuiki, Luca Benini
2020	J	`jnl`	Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads. CoRR Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
2020	—	`conf`	XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs. COOL CHIPS Dionysios Diamantopoulos, Florian Scheidegger, Stefan Mach, Fabian Schuiki, Germain Haugou, Michael Schaffner, Frank K. Gürkaynak, Christoph Hagleitner, A. Cristiano I. Malossi, Luca Benini
2019	C	`conf`	A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI. VLSI-SoC Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini
2019	J	`jnl`	A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets. IEEE Trans. Computers Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini
2019	J	`jnl`	Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI. CoRR Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini
2019	—	`conf`	NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI. ISOCC Fabian Schuiki, Michael Schaffner, Luca Benini
2019	A	`conf`	NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22 nm FD-SOI. DATE Fabian Schuiki, Michael Schaffner, Luca Benini
2019	J	`jnl`	Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. CoRR Fabian Schuiki, Florian Zaruba, Torsten Hoefler, Luca Benini
2019	—	`conf`	The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and Performance. ICECS Florian Zaruba, Fabian Schuiki, Stefan Mach, Luca Benini
2018	J	`jnl`	A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets. CoRR Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini
2018	J	`jnl`	NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22nm FD-SOI. CoRR Fabian Schuiki, Michael Schaffner, Luca Benini
2015	—	`conf`	Needle in a Haystack: Limiting the Search Space in Mission-aware Packet Forwarding for Drones. SmartObjects@MobiCom Mahdi Asadpour, Mario Burger, Fabian Schuiki, Karin Anna Hummel