F. Joel Ferguson

43 papers A* 1A 15C 1Misc 10Journal 13Unranked 3
YearRankTypeTitle / Venue / Authors
2007 J jnl
On state reduction of incompletely specified finite state machines.
Comput. Electr. Eng.
Sezer Gören, F. Joel Ferguson
2006 J jnl
Test sequence generation for controller verification and test with high coverage.
ACM Trans. Design Autom. Electr. Syst.
Sezer Gören, F. Joel Ferguson
2005 J jnl
Detection probabilities of interconnect breaks: an analysis.
Integr.
Shalini Ghosh, F. Joel Ferguson
2004 — conf
Estimating detection probability of interconnect opens using stuck-at tests.
ACM Great Lakes Symposium on VLSI
Shalini Ghosh, F. Joel Ferguson
2002 A conf
CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines.
DATE
Sezer Gören, F. Joel Ferguson
2002 A conf
Testing Finite State Machines Based on a Structural Coverage Metric .
ITC
Sezer Gören, F. Joel Ferguson
1999 Misc conf
A Systematic DFT Procedure for Library Cells.
VTS
Jingjing Xu, Rahul Kundu, F. Joel Ferguson
1999 A conf
Checking sequence generation for asynchronous sequential elements.
ITC
Sezer Gören, F. Joel Ferguson
1999 Misc conf
Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test.
VTS
Michael A. Margolese, F. Joel Ferguson
1998 Misc conf
A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric.
VTS
Douglas Williams, F. Joel Ferguson, Tracy Larrabee
1998 A conf
Cache RAM inductive fault analysis with fab defect modeling.
ITC
T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, F. Joel Ferguson, Jianlin Yu
1998 J jnl
Diagnosing realistic bridging faults with single stuck-at information.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
David B. Lavo, Brian Chess, Tracy Larrabee, F. Joel Ferguson
1998 A conf
On applying non-classical defect models to automated diagnosis.
ITC
Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess
1998 J jnl
Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haluk Konuk, F. Joel Ferguson
1997 Misc conf
A methodolgy for characterizing cell testability.
VTS
Alvin Jee, F. Joel Ferguson
1997 A conf
Bridging Fault Diagnosis in the Absence of Physical Information.
ITC
David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler
1997 A conf
Incorporating Physical Design-for-Test into Routing.
ITC
Richard McGowen, F. Joel Ferguson
1997 A conf
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits.
ITC
Haluk Konuk, F. Joel Ferguson
1996 Misc conf
An unexpected factor in testing for CMOS opens: the die surface.
VTS
Haluk Konuk, F. Joel Ferguson
1996 J jnl
Charge-based fault simulation for CMOS network breaks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haluk Konuk, F. Joel Ferguson, Tracy Larrabee
1996 J jnl
Detection of Multiple Faults in Two-Dimensional ILAs.
IEEE Trans. Computers
Martine D. F. Schlag, F. Joel Ferguson
1996 — conf
Maximum Likelihood Estimation for Yield Analysis.
DFT
F. Joel Ferguson, Jianlin Yu
1995 A* conf
Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks.
DAC
Haluk Konuk, F. Joel Ferguson, Tracy Larrabee
1995 A conf
Diagnosis of realistic bridging faults with single stuck-at information.
ICCAD
Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee
1994 — conf
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT.
EDAC-ETC-EUROASIC
Richard McGowen, F. Joel Ferguson
1994 A conf
Defect Classes - An Overdue Paradigm for CMOS IC.
ITC
Charles F. Hawkins, Jerry M. Soden, Alan W. Righter, F. Joel Ferguson
1994 Misc conf
Eliminating undetectable shorts between horizontal wires during channel routing.
VTS
Richard McGowen, F. Joel Ferguson
1994 A conf
Testing CMOS Logic Gates for Realistic Shorts.
ITC
Brian Chess, Anthony Freitas, F. Joel Ferguson, Tracy Larrabee
1993 Misc conf
Carafe: an inductive fault analysis tool for CMOS VLSI circuits.
VTS
Alvin Jee, F. Joel Ferguson
1993 Misc conf
Physical design for testability for bridges in CMOS circuits.
VTS
F. Joel Ferguson
1992 Misc conf
On the effectiveness of simultaneous self-test techniques.
VTS
Peter A. Johnson, F. Joel Ferguson
1991 A conf
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs.
ITC
F. Joel Ferguson, Tracy Larrabee
1991 Misc conf
Test pattern generation for current testable faults in static CMOS circuits.
VTS
F. Joel Ferguson, Tracy Larrabee
1990 J jnl
Detection of multiple faults in MOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
F. Joel Ferguson
1990 A conf
Testing for parametric faults in static CMOS circuits.
ITC
F. Joel Ferguson, Martin Taylor, Tracy Larrabee
1989 J jnl
Microprocessor Interfacing and the 68000: Peripherals and systems: Clements, A Wiley and Sons Ltd, Chichester, UK (1989) £39.95 pp 446.
Microprocess. Microsystems
F. Joel Ferguson
1988 J jnl
A CMOS fault extractor for inductive fault analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
F. Joel Ferguson, John Paul Shen
1988 J jnl
Book Review: Logic Design Principles by Edward J. McCluskey: Prentice-Hall Publishers, Englewood Cliffs, New Jersey, 549 pp., $39.95.
SIGARCH Comput. Archit. News
F. Joel Ferguson
1988 A conf
Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis.
ITC
John Paul Shen, F. Joel Ferguson
1985 J jnl
Inductive Fault Analysis of MOS Integrated Circuits.
IEEE Des. Test
John Paul Shen, Wojciech Maly, F. Joel Ferguson
1984 A conf
Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells.
ITC
Wojciech Maly, F. Joel Ferguson, John Paul Shen
1984 J jnl
The Design of Easily Tastabel VLSI Array Multipliers.
IEEE Trans. Computers
John Paul Shen, F. Joel Ferguson
1983 C conf
The design of two easily-testable VLSI array multipliers.
IEEE Symposium on Computer Arithmetic
F. Joel Ferguson, John Paul Shen