Ewout Martens - RankMe

57 papers A 6C 2Journal 23Unranked 25

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	11.5 A Compact 7b 175GS/s Linearized Time-Interleaved Slope ADC with Switched Input Buffers. ISSCC Ewout Martens, Angelo Parisi, Anirudh Kankuppe, Adam Cooman, Hanyue Li, Steven Van Winckel, Pratap Tumkur Renukaswamy, Lucas Moura Santana, Jorge Lagos, Nereo Markulic, Jan Craninckx
2026	J	`jnl`	A 7-bit 150-GSa/s DAC in 5-nm FinFET CMOS. IEEE J. Solid State Circuits Bart Moeneclaey, Joris Lambrecht, Angelo Parisi, Joris Van Kerrebrouck, Gertjan Coudyzer, Anirudh Kankuppe, Xin Yin, Ewout Martens, Jan Craninckx, Peter Ossieur
2024	—	`conf`	22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. ISSCC Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, SeHoon Park, Jorge-Luis Lagos, Nereo Markulic, Jan Craninckx
2024	—	`conf`	A 10GS/s Hierarchical Time-Interleaved ADC for RF-Sampling Applications. VLSI Technology and Circuits Nereo Markulic, Johan Nguyen, Jorge Luis Lagos-Benites, Ewout Martens, Jan Craninckx
2024	—	`conf`	A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS. VLSI Technology and Circuits Jorge Lagos, Pratap Tumkur Renukaswamy, Nereo Markulic, Ewout Martens, Jan Craninckx
2023	J	`jnl`	A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Rui Paulo Martins, Yan Zhu, Jan Craninckx, Chi-Hang Chan
2023	—	`conf`	A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET. MWSCAS Shun Nagata, Ewout Martens, Adam Cooman, Jan Craninckx
2023	—	`conf`	A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. ESSCIRC Lucas Moura Santana, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx
2023	—	`conf`	Calibration Techniques for Optimizing Performance of High-Speed ADCs. CICC Ewout Martens, Nereo Markulic, Jorge Luis Lagos-Benites, Jan Craninckx
2022	J	`jnl`	A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. IEEE J. Solid State Circuits Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx
2022	J	`jnl`	A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. IEEE J. Solid State Circuits Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
2022	J	`jnl`	A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2021	J	`jnl`	A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. IEEE J. Solid State Circuits Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2021	—	`conf`	A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. VLSI Circuits Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx
2021	J	`jnl`	A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. IEEE J. Solid State Circuits Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx
2021	—	`conf`	A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2021	—	`conf`	A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW. VLSI Circuits Ewout Martens, Davide Dermit, Mithlesh Shrivas, Shun Nagata, Jan Craninckx
2021	J	`jnl`	A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs Keigo Bunsen, Ewout Martens, Davide Dermit, Jan Craninckx
2021	—	`conf`	An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4 VLSI Circuits Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
2021	J	`jnl`	Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2020	—	`conf`	16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. ISSCC Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
2020	—	`conf`	A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2019	J	`jnl`	A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2019	—	`conf`	A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx
2019	J	`jnl`	A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
2019	—	`conf`	A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2019	J	`jnl`	A Compact Quad-Shank CMOS Neural Probe With 5, 120 Addressable Recording Sites and 384 Fully Differential Parallel Channels. IEEE Trans. Biomed. Circuits Syst. Shiwei Wang, Carolina Mora Lopez, Seyed Kasra Garakoui, Ho Sung Chun, Didac Gomez Salinas, Wim Sijbers, Jan Putzeys, Ewout Martens, Jan Craninckx, Nick Van Helleputte
2019	J	`jnl`	A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2018	—	`conf`	A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2018	—	`conf`	A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. VLSI Circuits Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
2018	J	`jnl`	A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. IEEE J. Solid State Circuits Ewout Martens, Benjamin P. Hershberg, Jan Craninckx
2016	—	`conf`	9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2016	J	`jnl`	A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. IEEE J. Solid State Circuits Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
2016	J	`jnl`	A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2015	—	`conf`	A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. ESSCIRC Barend van Liempd, Saneaki Ariumi, Ewout Martens, Shih-Hung Chen, Piet Wambacq, Jan Craninckx
2015	—	`conf`	A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5 ESSCIRC Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
2015	J	`jnl`	A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation. IEEE J. Solid State Circuits Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx
2014	J	`jnl`	A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration. IEEE J. Solid State Circuits Barend van Liempd, Jonathan Borremans, Ewout Martens, Sungwoo Cha, Hans Suys, Bob Verbruggen, Jan Craninckx
2013	—	`conf`	IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm. CICC Barend van Liempd, Jonathan Borremans, Sungwoo Cha, Ewout Martens, Hans Suys, Jan Craninckx
2012	J	`jnl`	RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert
2009	J	`jnl`	ANTIGONE: Top-down creation of analog-to-digital converter architectures. Integr. Ewout Martens, Georges G. E. Gielen
2008	J	`jnl`	Classification of analog synthesis tools based on their architecture selection mechanisms. Integr. Ewout Martens, Georges G. E. Gielen
2007	—	`conf`	Automated synthesis of complex analog circuits. ECCTD Georges G. E. Gielen, Tom Eeckelaert, Ewout Martens, Trent McConaghy
2007	—	`—`	High-level modeling and synthesis of analog integrated systems ; Hoog-niveau synthese van analoge geïntegreerde systemen. Ewout Martens
2006	C	`conf`	A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers. ISCAS Ewout Martens, Georges G. E. Gielen
2006	J	`jnl`	Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ewout Martens, Georges G. E. Gielen
2006	C	`conf`	Generic Behavioral Modeling of Analog and Mixed-Signal Systems. FDL Ewout Martens, Georges G. E. Gielen
2006	A	`conf`	Top-down heterogeneous synthesis of analog and mixed-signal systems. DATE Ewout Martens, Georges G. E. Gielen
2005	—	`conf`	Behavioral modeling and simulation of weakly nonlinear sampled-data systems. ISCAS (3) Ewout Martens, Georges G. E. Gielen
2005	A	`conf`	Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series. DATE Ewout Martens, Georges G. E. Gielen
2004	A	`conf`	A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design. DATE Ewout Martens, Georges G. E. Gielen
2004	J	`jnl`	An analytical integration method for the simulation of continuous-time ΔΣ modulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Georges G. E. Gielen, Kenneth Francken, Ewout Martens, Martin Vogels
2004	—	`conf`	High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models. ASP-DAC Ewout Martens, Georges G. E. Gielen
2003	A	`conf`	A Model of Computation for Continuous-Time ?-? Modulators. DATE Ewout Martens, Georges G. E. Gielen
2002	A	`conf`	A behavioral simulation tool for continuous-time delta sigma modulators. ICCAD Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen
2002	A	`conf`	DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators. DATE Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen
2002	—	`conf`	Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration. ISCAS (4) Martin Vogels, Kenneth Francken, Ewout Martens, Georges G. E. Gielen