Evangeline F. Y. Young

223 papers A* 28A 43B 3C 1Misc 2Journal 76Unranked 64

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An Open-Source High-Concurrency and High-Performance Parallel Router for UltraScale FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wenhao Lin, Xinshi Zang, Zewen Li, Evangeline F. Y. Young
2026	J	`jnl`	Efficient and Effective E-graph-based Logic Optimization. ACM Trans. Design Autom. Electr. Syst. Tianji Liu, Nutdranai Jaruthikorn, Shiju Lin, Bentian Jiang, Guannan Guo, Weihua Sheng, Evangeline F. Y. Young
2026	—	`conf`	Gradient-Guided RC Weighting for Timing-Driven Global Routing. ISPD Liang Xiao, Qinkai Duan, Leilei Jin, Jinwei Liu, Tsung-Yi Ho, Evangeline F. Y. Young, Martin D. F. Wong
2026	J	`jnl`	InstantGR: Scalable GPU Parallelization for 3-D Global Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Liang Xiao, Shiju Lin, Jinwei Liu, Qinkai Duan, Tsung-Yi Ho, Evangeline F. Y. Young
2026	J	`jnl`	MALT: ML Assisted Shallow-Light Tree Construction. ACM Trans. Design Autom. Electr. Syst. Liang Xiao, Jinwei Liu, Lixin Liu, Qijing Wang, Evangeline F. Y. Young, Martin D. F. Wong
2026	A	`conf`	RND: A Mixed-Grained Parallel Routing Framework with Region-based Net Decomposition for UltraScale FPGAs. FPGA Wenhao Lin, Zewen Li, Xinshi Zang, Evangeline F. Y. Young
2026	J	`jnl`	TroLLoc: Security Closure against Hardware Trojans by Logic Locking and Layout Hardening. J. Hardw. Syst. Secur. Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F. Y. Young, Johann Knechtel
2025	J	`jnl`	A Unified Parallel Framework for LUT Mapping and Logic Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tianji Liu, Yang Sun, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young
2025	—	`conf`	Dr. Guide: AI-Guided Detailed Routing. MLCAD Qijing Wang, Wing Ho Lau, Tsung-Yi Ho, Evangeline F. Y. Young, Martin D. F. Wong
2025	A	`conf`	ExactMap: Enhancing Delay Optimization in Parallel ASIC Technology Mapping. ICCAD Zhenxuan Xie, Lixin Liu, Tianji Liu, Evangeline F. Y. Young
2025	A	`conf`	Fast Dynamic IR-Drop Prediction with Dual-Path Spatial-Temporal Attention. DATE Bangqi Fu, Lixin Liu, Qijing Wang, Yutao Wang, Martin D. F. Wong, Evangeline F. Y. Young
2025	—	`conf`	Invited: AI-assisted Routing. ISPD Qijing Wang, Liang Xiao, Evangeline F. Y. Young
2025	—	`conf`	POAgent: A Multi-agent Controller Towards Adaptive Parameter Optimization. KSEM (1) Qijing Wang, Martin D. F. Wong, Evangeline F. Y. Young
2025	A*	`conf`	Simulation-based Parallel Sweeping: A New Perspective on Combinational Equivalence Checking. DAC Tianji Liu, Evangeline F. Y. Young
2025	A*	`conf`	SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding. DAC Chengxi Li, Yang Sun, Lei Chen, Yiwen Wang, Mingxuan Yuan, Evangeline F. Y. Young
2025	J	`jnl`	SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding. CoRR Chengxi Li, Yang Sun, Lei Chen, Yiwen Wang, Mingxuan Yuan, Evangeline F. Y. Young
2025	B	`conf`	TRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro Placer. FPL Qin Luo, Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong
2025	J	`jnl`	Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Trans. Cryptogr. Hardw. Embed. Syst. Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini
2024	—	`conf`	A Multi-agent Generative Model for Collaborative Global Routing Refinement. ACM Great Lakes Symposium on VLSI Qijing Wang, Jinwei Liu, Martin D. F. Wong, Evangeline F. Y. Young
2024	Misc	`conf`	A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints. FCCM Qin Luo, Xinshi Zang, Qijing Wang, Fangzhou Wang, Evangeline F. Y. Young, Martin D. F. Wong
2024	—	`conf`	Accelerating Physical Design from 1 to N. ISPD Evangeline F. Y. Young
2024	—	`conf`	An Open-Source Fast Parallel Routing Approach for Commercial FPGAs. ACM Great Lakes Symposium on VLSI Xinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young
2024	J	`jnl`	An Open-Source Fast Parallel Routing Approach for Commercial FPGAs. CoRR Xinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young
2024	B	`conf`	CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs. ASPDAC Bangqi Fu, Lixin Liu, Yang Sun, Wing Ho Lau, Martin D. F. Wong, Evangeline F. Y. Young
2024	—	`conf`	ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation. ACM Great Lakes Symposium on VLSI Qijing Wang, Xiaopeng Zhang, Martin D. F. Wong, Evangeline F. Y. Young
2024	—	`conf`	Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing. ACM Great Lakes Symposium on VLSI Xinshi Zang, Qin Luo, Zhongwei Shao, Jifeng Zhang, Evangeline F. Y. Young, Martin D. F. Wong
2024	J	`jnl`	Erratum to: Large circuit models: opportunities and challenges. Sci. China Inf. Sci. Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024	J	`jnl`	FastPass: A Fast Pin Access Analysis Framework for Detailed Routability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fangzhou Wang, Jinwei Liu, Wing Ho Lau, Haocheng Li, Evangeline F. Y. Young
2024	B	`conf`	FineMap: A Fine-grained GPU-parallel LUT Mapping Engine. ASPDAC Tianji Liu, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young
2024	A*	`conf`	GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis. DAC Shiju Lin, Guannan Guo, Tsung-Wei Huang, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong
2024	A	`conf`	Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration. ICCAD Bangqi Fu, Lixin Liu, Martin D. F. Wong, Evangeline F. Y. Young
2024	A	`conf`	InstantGR: Scalable GPU Parallelization for Global Routing. ICCAD Shiju Lin, Liang Xiao, Jinwei Liu, Evangeline F. Y. Young
2024	J	`jnl`	Large circuit models: opportunities and challenges. Sci. China Inf. Sci. Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024	A*	`conf`	Massively Parallel AIG Resubstitution. DAC Yang Sun, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young
2024	—	`conf`	On Advanced Methodologies for Microarchitecture Design Space Exploration. ACM Great Lakes Symposium on VLSI Tianji Liu, Qijing Wang, Lixin Liu, Fangzhou Wang, Evangeline F. Y. Young
2024	J	`jnl`	Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lixin Liu, Tianji Liu, Bentian Jiang, Evangeline F. Y. Young
2024	A	`conf`	Potter: A Parallel Overlap-Tolerant Router for UltraScale FPGAs. ICCAD Xinshi Zang, Wenhao Lin, Jinwei Liu, Evangeline F. Y. Young
2024	J	`jnl`	Recap of the 42nd Edition of the International Conference on Computer- Aided Design (ICCAD 2023). IEEE Des. Test Evangeline F. Y. Young
2024	A*	`conf`	Size-Optimized Depth-Constrained Large Parallel Prefix Circuits. DAC Shiju Lin, Bentian Jiang, Weihua Sheng, Evangeline F. Y. Young
2024	J	`jnl`	The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024	J	`jnl`	TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans. CoRR Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F. Y. Young, Johann Knechtel
2024	J	`jnl`	Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Cryptol. ePrint Arch. Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini
2024	J	`jnl`	Xplace: An Extremely Fast and Extensible Placement Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lixin Liu, Bangqi Fu, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong
2023	—	`conf`	An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems. ASP-DAC Dan Zheng, Evangeline F. Y. Young
2023	—	`conf`	CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. ACM Great Lakes Symposium on VLSI Xinshi Zang, Lei Chen, Xing Li, Wilson W. K. Thong, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong
2023	A*	`conf`	EDGE: Efficient DAG-based Global Routing Engine. DAC Jinwei Liu, Evangeline F. Y. Young
2023	J	`jnl`	Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bentian Jiang, Xinshi Zang, Martin D. F. Wong, Evangeline F. Y. Young
2023	—	`conf`	FastPass: Fast Pin Access Analysis with Incremental SAT Solving. ISPD Fangzhou Wang, Jinwei Liu, Evangeline F. Y. Young
2023	J	`jnl`	GAMER: GPU-Accelerated Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong
2023	—	`conf`	GPU Acceleration in Physical Synthesis. ISPD Evangeline F. Y. Young
2023	J	`jnl`	PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young
2023	A*	`conf`	Rethinking AIG Resynthesis in Parallel. DAC Tianji Liu, Evangeline F. Y. Young
2023	—	`conf`	SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems. ACM Great Lakes Symposium on VLSI Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong
2023	—	`conf`	Security Closure of IC Layouts Against Hardware Trojans. ISPD Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young
2022	A*	`conf`	A2-ILT: GPU accelerated ILT with spatial attention mechanism. DAC Qijing Wang, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young
2022	J	`jnl`	CU.POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young
2022	—	`conf`	Challenges and Approaches in VLSI Routing. ISPD Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan
2022	J	`jnl`	Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bentian Jiang, Lixin Liu, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
2022	A*	`conf`	NovelRewrite: node-level parallel AIG rewriting. DAC Shiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young
2022	A*	`conf`	Partition and place finite element model on wafer-scale engine. DAC Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young
2022	J	`jnl`	Pin-Accessible Legalization for Mixed-Cell-Height Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haocheng Li, Wing-Kai Chow, Gengjie Chen, Bei Yu, Evangeline F. Y. Young
2022	A	`ed.`	Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022 ICCAD Tulika Mitra, Evangeline F. Y. Young, Jinjun Xiong
2022	A	`conf`	RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement. ITC Xiaopeng Zhang, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Evangeline F. Y. Young, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao
2022	J	`jnl`	Security Closure of IC Layouts Against Hardware Trojans. CoRR Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young
2022	A*	`conf`	Xplace: an extremely fast and extensible global placement framework. DAC Lixin Liu, Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young
2021	—	`conf`	Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method. ASP-DAC Haoyu Yang, Shifan Zhang, Kang Liu, Siting Liu, Benjamin Tan, Ramesh Karri, Siddharth Garg, Bei Yu, Evangeline F. Y. Young
2021	A*	`conf`	Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation. DAC Xiaopeng Zhang, Haoyu Yang, Evangeline F. Y. Young
2021	—	`conf`	Building up End-to-end Mask Optimization Framework with Self-training. ISPD Bentian Jiang, Xiaopeng Zhang, Lixin Liu, Evangeline F. Y. Young
2021	J	`jnl`	Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haocheng Li, Satwik Patnaik, Mohammed Ashraf, Haoyu Yang, Johann Knechtel, Bei Yu, Ozgur Sinanoglu, Evangeline F. Y. Young
2021	—	`conf`	Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. ASP-DAC Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young
2021	A*	`conf`	REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning. DAC Jinwei Liu, Gengjie Chen, Evangeline F. Y. Young
2020	J	`jnl`	Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection. ACM Trans. Design Autom. Electr. Syst. Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg
2020	J	`jnl`	Attacking Split Manufacturing from a Deep Learning Perspective. CoRR Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu
2020	A	`conf`	CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing. ICCAD Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young
2020	A*	`conf`	CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. DAC Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young
2020	J	`jnl`	Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gengjie Chen, Chak-Wa Pui, Haocheng Li, Evangeline F. Y. Young
2020	J	`jnl`	GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haoyu Yang, Shuhe Li, Zihao Deng, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
2020	J	`jnl`	Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ACM Trans. Design Autom. Electr. Syst. Chak-Wa Pui, Evangeline F. Y. Young
2020	A	`conf`	Layout Pattern Generation and Legalization with Generative Learning Models. ICCAD Xiaopeng Zhang, James P. Shiely, Evangeline F. Y. Young
2020	A	`conf`	Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization. ICCAD Bentian Jiang, Lixin Liu, Yuzhe Ma, Hang Zhang, Bei Yu, Evangeline F. Y. Young
2020	A	`conf`	PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning. ICCAD Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young
2020	J	`jnl`	SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gengjie Chen, Evangeline F. Y. Young
2020	J	`jnl`	Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young
2019	—	`conf`	A fast machine learning-based mask printability predictor for OPC acceleration. ASP-DAC Bentian Jiang, Hang Zhang, Jinglei Yang, Evangeline F. Y. Young
2019	—	`conf`	An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems. SLIP Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young
2019	J	`jnl`	Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection. CoRR Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg
2019	A*	`conf`	Attacking Split Manufacturing from a Deep Learning Perspective. DAC Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu
2019	—	`conf`	Detailed routing by sparse grid graph and minimum-area-captured path search. ASP-DAC Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young
2019	A	`conf`	Dim Sum: Light Clock Tree by Small Diameter Sum. DATE Gengjie Chen, Evangeline F. Y. Young
2019	A	`conf`	Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction. ICCAD Haocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen, Evangeline F. Y. Young
2019	A*	`conf`	FIT: Fill Insertion Considering Timing. DAC Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F. Y. Young, Bei Yu
2019	J	`jnl`	Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jian Kuang, Evangeline F. Y. Young
2019	A	`conf`	Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ICCAD Chak-Wa Pui, Evangeline F. Y. Young
2019	J	`jnl`	Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
2019	A*	`conf`	MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses. DAC Jingsong Chen, Jinwei Liu, Gengjie Chen, Dan Zheng, Evangeline F. Y. Young
2019	—	`conf`	Session details: Patterning and Machine Learning. ISPD Evangeline F. Y. Young
2019	J	`jnl`	Three-dimensional Floorplan Representations by Using Corner Links and Partial Order. ACM Trans. Design Autom. Electr. Syst. Ilgweon Kang, Fang Qiao, Dongwon Park, Daniel Kane, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham
2018	—	`conf`	A two-step search engine for large scale boolean matching under NP3 equivalence. ASP-DAC Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young
2018	J	`jnl`	CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jian Kuang, Evangeline F. Y. Young, Bei Yu
2018	Misc	`conf`	Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. FCCM Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang
2018	A*	`conf`	GAN-OPC: mask optimization with lithography-guided generative adversarial nets. DAC Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
2018	J	`jnl`	RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu
2018	A*	`conf`	Routability-driven and fence-aware legalization for mixed-cell-height circuits. DAC Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu
2018	J	`jnl`	STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jian Kuang, Junjie Ye, Evangeline F. Y. Young
2018	—	`conf`	Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration. ACM Great Lakes Symposium on VLSI Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young
2017	—	`conf`	Bilinear Lithography Hotspot Detection. ISPD Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu
2017	A	`conf`	Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). ICCAD Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu
2017	—	`conf`	Fence-aware detailed-routability driven placement. SLIP Wing-Kai Chow, Jian Kuang, Peishan Tu, Evangeline F. Y. Young
2017	A*	`conf`	Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond. DAC Jian Kuang, Evangeline F. Y. Young
2017	A*	`conf`	Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning. DAC Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young
2017	—	`conf`	Lithography hotspot detection: From shallow to deep learning. SoCC Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young
2017	A*	`conf`	Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design. DAC Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu
2017	A	`conf`	SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm. ICCAD Gengjie Chen, Peishan Tu, Evangeline F. Y. Young
2017	—	`conf`	Timing driven routing tree construction. SLIP Peishan Tu, Wing-Kai Chow, Evangeline F. Y. Young
2016	J	`jnl`	An Effective Chemical Mechanical Polishing Fill Insertion Approach. ACM Trans. Design Autom. Electr. Syst. Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young
2016	A	`conf`	Enabling online learning in lithography hotspot detection with information-theoretic feature optimization. ICCAD Hang Zhang, Bei Yu, Evangeline F. Y. Young
2016	A	`conf`	Incorporating cut redistribution with mask assignment to enable 1D gridded design. ICCAD Jian Kuang, Evangeline F. Y. Young, Bei Yu
2016	A*	`conf`	Legalization algorithm for multiple-row height standard cell design. DAC Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young
2016	A	`conf`	Optimization for Multiple Patterning Lithography with cutting process and beyond. DATE Jian Kuang, Evangeline F. Y. Young
2016	J	`jnl`	Placement: From Wirelength to Detailed Routability. IPSJ Trans. Syst. LSI Des. Methodol. Wing-Kai Chow, Evangeline F. Y. Young
2016	J	`jnl`	Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology. ACM Trans. Design Autom. Electr. Syst. Evangeline F. Y. Young, Azadeh Davoodi
2016	—	`ed.`	Proceedings of the 2016 on International Symposium on Physical Design, ISPD 2016, Santa Rosa, CA, USA, April 3-6, 2016 ISPD Evangeline F. Y. Young, Mustafa Ozdal
2016	J	`jnl`	Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement. ACM Trans. Design Autom. Electr. Syst. Xu He, Yao Wang, Yang Guo, Evangeline F. Y. Young
2016	A	`conf`	RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. ICCAD Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu
2016	J	`jnl`	Row-structure stencil planning approaches for E-beam lithography with overlapped characters. Integr. Jian Kuang, Evangeline F. Y. Young
2016	—	`conf`	Simultaneous template optimization and mask assignment for DSA with multiple patterning. ASP-DAC Jian Kuang, Junjie Ye, Evangeline F. Y. Young
2016	—	`ch.`	Slicing Floorplan Orientation. Encyclopedia of Algorithms Evangeline F. Y. Young
2016	J	`jnl`	Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs. IEEE Trans. Very Large Scale Integr. Syst. Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young
2016	—	`conf`	VLSI layout hotspot detection based on discriminative feature extraction. APCCAS Hang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young
2015	A	`conf`	A robust approach for process variation aware mask optimization. DATE Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young
2015	—	`conf`	An Effective Chemical Mechanical Polishing Filling Approach. ISVLSI Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young
2015	A	`conf`	An effective triple patterning aware grid-based detailed routing approach. DATE Zhiqing Liu, Chuangwen Liu, Evangeline F. Y. Young
2015	J	`jnl`	Planning Massive Interconnects in 3-D Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Johann Knechtel, Evangeline F. Y. Young, Jens Lienig
2015	—	`ed.`	Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29 - April 1, 2015 ISDP Azadeh Davoodi, Evangeline F. Y. Young
2014	—	`conf`	A Fast Hypergraph Bipartitioning Algorithm. ISVLSI Wenzan Cai, Evangeline F. Y. Young
2014	—	`conf`	A highly-efficient row-structure stencil planning approach for e-beam lithography with overlapped characters. ISPD Jian Kuang, Evangeline F. Y. Young
2014	A	`conf`	A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only). FPGA Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young
2014	—	`conf`	Cell density-driven detailed placement with displacement constraint. ISPD Wing-Kai Chow, Jian Kuang, Xu He, Wenzan Cai, Evangeline F. Y. Young
2014	—	`conf`	General purpose cross-referencing Microfluidic Biochip with reduced pin-count. ASP-DAC Jackson H. C. Yeung, Evangeline F. Y. Young
2014	J	`jnl`	Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach. Integr. Wing-Kai Chow, Liang Li, Evangeline F. Y. Young, Chiu-Wing Sham
2014	A	`conf`	Overlapping-aware throughput-driven stencil planning for E-beam lithography. ICCAD Jian Kuang, Evangeline F. Y. Young
2014	C	`conf`	Reducing pin count on cross-referencing Digital Microfluidic Biochip. ISCAS Ho Chuen Jackson Yeung, Evangeline F. Y. Young, Chiu-sing Choy
2014	—	`conf`	Structural planning of 3D-IC interconnects by block alignment. ASP-DAC Johann Knechtel, Evangeline F. Y. Young, Jens Lienig
2014	A	`conf`	Triple patterning lithography aware optimization for standard cell based design. ICCAD Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young
2013	A*	`conf`	An efficient layout decomposition approach for triple patterning lithography. DAC Jian Kuang, Evangeline F. Y. Young
2013	J	`jnl`	ObSteiner: An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees in the Presence of Complex Rectilinear Obstacles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tao Huang, Evangeline F. Y. Young
2013	A*	`conf`	Ripple 2.0: high quality routability-driven placement via global router integration. DAC Xu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Wenzan Cai, Evangeline F. Y. Young
2013	J	`jnl`	Ripple: A Robust and Effective Routability-Driven Placer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Evangeline F. Y. Young
2013	—	`conf`	SRP: simultaneous routing and placement for congestion refinement. ISPD Xu He, Wing-Kai Chow, Evangeline F. Y. Young
2012	A	`conf`	Construction of rectilinear Steiner minimum trees with slew constraints over obstacles. ICCAD Tao Huang, Evangeline F. Y. Young
2012	—	`conf`	Crosslink insertion for variation-driven clock network construction. ACM Great Lakes Symposium on VLSI Fuqiang Qian, Haitong Tian, Evangeline F. Y. Young
2012	J	`jnl`	Postgrid Clock Routing for High Performance Microprocessor Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze
2012	J	`jnl`	Postplacement Voltage Island Generation. ACM Trans. Design Autom. Electr. Syst. Mario K. Y. Leung, Eric K. I. Chio, Evangeline F. Y. Young
2011	A	`conf`	A monte-carlo floating-point unit for self-validating arithmetic. FPGA Jackson H. C. Yeung, Evangeline F. Y. Young, Philip Heng Wai Leong
2011	—	`conf`	A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing. ASP-DAC Qiang Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young
2011	A*	`conf`	An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles. DAC Tao Huang, Evangeline F. Y. Young
2011	A*	`conf`	An optimal algorithm for layer assignment of bus escape routing on PCBs. DAC Qiang Ma, Evangeline F. Y. Young, Martin D. F. Wong
2011	J	`jnl`	Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham
2011	—	`conf`	Grid-to-ports clock routing for high performance microprocessor designs. ISPD Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze
2011	J	`jnl`	MSV-Driven Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qiang Ma, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou
2011	J	`jnl`	On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tao Huang, Liang Li, Evangeline F. Y. Young
2011	J	`jnl`	Placement and Routing for Cross-Referencing Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zigang Xiao, Evangeline F. Y. Young
2011	A	`conf`	Ripple: An effective routability-driven placer by iterative cell movement. ICCAD Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui, Evangeline F. Y. Young
2011	J	`jnl`	Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qiang Ma, Linfu Xiao, Yiu-Cheong Tam, Evangeline F. Y. Young
2010	—	`conf`	A dual-MST approach for clock network synthesis. ASP-DAC Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young
2010	J	`jnl`	Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness. ACM Trans. Design Autom. Electr. Syst. Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng
2010	—	`conf`	CrossRouter: a droplet router for cross-referencing digital microfluidic biochips. ASP-DAC Zigang Xiao, Evangeline F. Y. Young
2010	—	`conf`	Droplet-routing-aware module placement for cross-referencing biochips. ISPD Zigang Xiao, Evangeline F. Y. Young
2010	—	`conf`	Fixed-outline thermal-aware 3D floorplanning. ASP-DAC Linfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F. Y. Young
2010	A	`conf`	Local clock skew minimization using blockage-aware mixed tree-mesh clock network. ICCAD Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, Evangeline F. Y. Young
2010	J	`jnl`	Multivoltage Floorplan Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qiang Ma, Evangeline F. Y. Young
2010	A	`conf`	Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach. ICCAD Tao Huang, Evangeline F. Y. Young
2010	—	`conf`	Physical synthesis of bus matrix for high bandwidth low power on-chip communications. ISPD Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng
2010	A	`conf`	Practical placement and routing techniques for analog circuit designs. ICCAD Linfu Xiao, Evangeline F. Y. Young, Xiao-Yong He, Kong-Pang Pun
2009	—	`conf`	Analog placement with common centroid and 1-D symmetry constraints. ASP-DAC Linfu Xiao, Evangeline F. Y. Young
2009	J	`jnl`	Block flipping and white space distribution for wirelength minimization. Integr. Chiu-Wing Sham, Evangeline F. Y. Young
2009	J	`jnl`	Congestion prediction in early stages of physical design. ACM Trans. Design Autom. Electr. Syst. Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu
2009	A	`conf`	Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree. ICCAD Liang Li, Zaichen Qian, Evangeline F. Y. Young
2009	J	`jnl`	Handling routability in floorplan design with twin binary trees. Integr. Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu
2009	—	`conf`	Multi-voltage floorplan design with optimal voltage assignment. ISPD Zaichen Qian, Evangeline F. Y. Young
2008	—	`conf`	3-D floorplanning using labeled tree and dual sequences. ISPD Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng
2008	—	`ch.`	Floorplan Representations. Handbook of Algorithms for Physical Design Automation Evangeline F. Y. Young
2008	—	`ch.`	Global Interconnect Planning. Handbook of Algorithms for Physical Design Automation Cheng-Kok Koh, Evangeline F. Y. Young, Yao-Wen Chang
2008	J	`jnl`	Multi-bend bus driven floorplanning. Integr. Jill H. Y. Law, Evangeline F. Y. Young
2008	A	`conf`	Network flow-based power optimization under timing constraints in MSV-driven floorplanning. ICCAD Qiang Ma, Evangeline F. Y. Young
2008	A	`conf`	Obstacle-avoiding rectilinear Steiner tree construction. ICCAD Liang Li, Evangeline F. Y. Young
2008	J	`jnl`	Optimizing wirelength and routability by searching alternative packings in floorplanning. ACM Trans. Design Autom. Electr. Syst. Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou
2008	—	`ch.`	Slicing Floorplan Orientation. Encyclopedia of Algorithms Evangeline F. Y. Young
2008	—	`conf`	TCG-based multi-bend bus driven floorplanning. ASP-DAC Tilen Ma, Evangeline F. Y. Young
2007	A	`conf`	Analog placement with common centroid constraints. ICCAD Qiang Ma, Evangeline F. Y. Young, Kong-Pang Pun
2007	J	`jnl`	Area reduction by deadspace utilization on interconnect optimized floorplan. ACM Trans. Design Autom. Electr. Syst. Chiu-Wing Sham, Evangeline F. Y. Young
2007	A	`conf`	Voltage island-driven floorplanning. ICCAD Qiang Ma, Evangeline F. Y. Young
2007	J	`jnl`	Wire Retiming Problem With Net Topology Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu
2006	A	`conf`	Analog placement with symmetry and other placement constraints. ICCAD Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu
2006	—	`conf`	Block alignment in 3D floorplan using layered TCG. ACM Great Lakes Symposium on VLSI Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching
2006	A*	`conf`	Optimal cell flipping in placement and floorplanning. DAC Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu
2006	A	`conf`	Post-placement voltage island generation. ICCAD Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu
2006	—	`conf`	Shuttle mask floorplanning with modified alpha-restricted grid. ACM Great Lakes Symposium on VLSI Royce L. S. Ching, Evangeline F. Y. Young
2005	—	`conf`	Congestion prediction in early stages. SLIP Chiu-Wing Sham, Evangeline F. Y. Young
2005	—	`conf`	Congestion prediction in floorplanning. ASP-DAC Chiu-Wing Sham, Evangeline F. Y. Young
2005	—	`conf`	Multi-bend bus driven floorplanning. ISPD Jill H. Y. Law, Evangeline F. Y. Young
2004	J	`jnl`	Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chris C. N. Chu, Evangeline F. Y. Young
2004	—	`conf`	Performance-driven register insertion in placement. ISPD Dennis K. Y. Tong, Evangeline F. Y. Young
2004	J	`jnl`	Placement constraints in floorplan design. IEEE Trans. Very Large Scale Integr. Syst. Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
2003	A	`conf`	A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. DATE Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu
2003	—	`conf`	Clustering based acyclic multi-way partitioning. ACM Great Lakes Symposium on VLSI Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak
2003	—	`conf`	Fast buffer planning and congestion optimization in interconnect-driven floorplanning. ASP-DAC Keith W. C. Wong, Evangeline F. Y. Young
2003	—	`conf`	Interconnect-driven floorplanning by searching alternative packings. ASP-DAC Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou
2003	A	`conf`	Retiming with Interconnect and Gate Delay. ICCAD Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu
2003	J	`jnl`	Routability-driven floorplanner with buffer block planning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chiu-Wing Sham, Evangeline F. Y. Young
2003	J	`jnl`	Slicing floorplan with clustering constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wing Seung Yuen, Evangeline F. Y. Young
2003	J	`jnl`	Temporal logic replication for dynamically reconfigurable FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wai-Kei Mak, Evangeline F. Y. Young
2003	J	`jnl`	Twin binary sequences: a nonredundant representation for general nonslicing floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen
2002	—	`conf`	A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. ASP-DAC/VLSI Design Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
2002	A	`conf`	Congestion Estimation with Buffer Planning in Floorplan Design. DATE Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young
2002	A	`conf`	Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. DATE Chris C. N. Chu, Evangeline F. Y. Young
2002	—	`conf`	Routability driven floorplanner with buffer block planning. ISPD Chiu-Wing Sham, Evangeline F. Y. Young
2002	—	`conf`	Temporal logic replication for dynamically reconfigurable FPGA partitioning. ISPD Wai-Kei Mak, Evangeline F. Y. Young
2002	—	`conf`	Twin binary sequences: a non-redundant representation for general non-slicing floorplan. ISPD Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen
2001	J	`jnl`	Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong
2001	J	`jnl`	On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
2000	J	`jnl`	Slicing floorplans with range constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
1999	J	`jnl`	Slicing floorplans with boundary constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang