Eugenio Villar

92 papers A* 1A 4B 4C 26Misc 3Journal 25Unranked 23

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	AI-based estimation of embedded software execution cycles in host-compiled simulation. DCIS Raúl Gómez-Varela, David Aledo, Héctor Posadas, Eugenio Villar
2023	—	`conf`	Automatic code generation from UML for data memory optimization in microcontrollers. DCIS Héctor Posadas, José Luis Vázquez, Eugenio Villar
2023	—	`conf`	Towards a European Network of Enabling Technologies for Drones. DroneSE/RAPIDO@HiPEAC Réda Nouacer, Mahmoud Hussein, Paul Detterer, Eugenio Villar, Fernando Herrera, Carlo Tieri, Emmanuel Grolleau
2021	J	`jnl`	Key technologies for safe and autonomous drones. Microprocess. Microsystems Mahmoud Hussein, Réda Nouacer, Federico Corradi, Yassine Ouhammou, Eugenio Villar, Carlo Tieri, Rodrigo Castiñeira
2021	C	`conf`	Modeling and Performance Estimation of Robotic Systems using ROS: Application to drone-based Services. FDL Javier Merino, Raul Gomez, Hector Posadas, Eugenio Villar
2021	—	`conf`	Multilevel host-compiled simulation framework for ROS-based UAV services using ArduCopter. DCIS Javier Merino, Raul Gomez, Hector Posadas, Eugenio Villar
2020	—	`conf`	Data flow analysis from UML/MARTE models based on binary traces. DCIS Héctor Posadas, Javier Merino, Eugenio Villar
2020	C	`conf`	Key Enabling Technologies for Drones. DSD Mahmoud Hussein, Réda Nouacer, Yassine Ouhammou, Eugenio Villar, Federico Corradi, Carlo Tieri, Rodrigo Castiñeira
2020	J	`jnl`	Mega-modeling of complex, distributed, heterogeneous CPS systems. Microprocess. Microsystems Eugenio Villar, Javier Merino, Hector Posadas, Rafik Henia, Laurent Rioux
2020	C	`conf`	Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow. DSD Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Hector Posadas, Javier Merino, Eugenio Villar
2019	—	`conf`	Accelerating Host-Compiled Simulation by Modifying IR Code: Industrial application in the spatial domain. DCIS Héctor Posadas, Eugenio Villar, Manuel Sanchez-Renedo
2017	J	`jnl`	CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. Microprocess. Microsystems Kim Grüttner, Ralph Görgen, Sören Schreiner, Fernando Herrera, Pablo Peñil, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Emanuele Vitali, Davide Zoni, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander, Kathrin Rosvall, Nima Khalilzad, Davide Quaglia
2017	—	`ch.`	Modeling Hardware/Software Embedded Systems with UML/MARTE: A Single-Source Design Approach. Handbook of Hardware/Software Codesign Fernando Herrera, Julio L. Medina, Eugenio Villar
2017	J	`jnl`	Special issue on: "Heterogeneous architectures for Cyber-physical systems (HACPS)". Microprocess. Microsystems Houcine Hassan, Laurence T. Yang, Jason Xue, Eugenio Villar
2017	C	`conf`	Static Write Buffer Cache Modeling to Increase Host-Compiled Simulation Accuracy. DSD Hector Posadas, Luis Diaz, Eugenio Villar
2016	C	`conf`	CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties. DSD Ralph Görgen, Kim Grüttner, Fernando Herrera, Pablo Peñil, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander, Kathrin Rosvall, Davide Quaglia
2016	J	`jnl`	Using Professional Resources for Teaching Embedded SW Development. Rev. Iberoam. de Tecnol. del Aprendiz. Hector Posadas, Eugenio Villar
2015	C	`conf`	A model-based, single-source approach to design-space exploration and synthesis of mixed-criticality systems. SCOPES Fernando Herrera, Pablo Peñil, Eugenio Villar
2015	J	`jnl`	Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics. J. Syst. Archit. Héctor Posadas, Pablo Peñil, Alejandro Nicolás, Eugenio Villar
2015	C	`conf`	Enhancing analysability and time predictability in UML/MARTE component-based application models. FDL Fernando Herrera, Pablo Peñil, Eugenio Villar
2015	J	`jnl`	Innovative circuit and system design methodologies for green cyber-physical systems. Microprocess. Microsystems Jiafu Wan, Chin-Feng Lai, Shiwen Mao, Eugenio Villar, Subhas Mukhopadhyay
2014	—	`conf`	A framework for design space exploration and performance analysis of networked embedded systems. RAPIDO Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia, Hector Posadas, Eugenio Villar
2014	C	`conf`	Automatic Synthesis over Multiple APIs from Uml/Marte Models for Easy Platform Mapping and Reuse. DSD Alejandro Nicolás, Pablo Peñil, Héctor Posadas, Eugenio Villar
2014	J	`jnl`	Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation. Microelectron. J. Héctor Posadas, Pablo Peñil, Alejandro Nicolás, Eugenio Villar
2014	J	`jnl`	Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project. Microprocess. Microsystems Héctor Posadas, Alejandro Nicolás, Pablo Peñil, Eugenio Villar, Florian Broekaert, Michel Bourdellès, Albert Cohen, Mihai T. Lazarescu, Luciano Lavagno, Andrei Sergeevich Terechko, Miguel Glassee, Manuel Prieto
2014	J	`jnl`	The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems. J. Syst. Archit. Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia, Gianluca Palermo
2013	C	`conf`	EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time Applications. DSD Hector Posadas, Eugenio Villar, Florian Broekaert, Michel Bourdellès, Albert Cohen, Antoniu Pop, Nhat Minh Lê, Adrien Guatto, Mihai T. Lazarescu, Luciano Lavagno, Andrei Sergeevich Terechko, Miguel Glassee, Daniel Calvo, Eduardo de las Heras
2013	C	`conf`	Early Performance Evaluation of Multi-OS Embedded Platforms Using Native Simulation. DSD Rodrigo Fernández, Hector Posadas, Eugenio Villar
2013	J	`jnl`	The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration. Microprocess. Microsystems Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia, Francisco Ferrero, Raúl Valencia
2012	Misc	`conf`	A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models. CODES+ISSS Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia
2012	C	`conf`	A model-driven methodology for the development of SystemC executable environments. FDL Fernando Herrera, Pablo Peñil, Hector Posadas, Eugenio Villar
2012	—	`conf`	Automatic synthesis from UML/MARTE models using channel semantics. ACES-MB@MoDELS Pablo Peñil, Héctor Posadas, Alejandro Nicolás, Eugenio Villar
2012	C	`conf`	COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration. DSD Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia, Francisco Ferrero, Raúl Valencia
2012	C	`conf`	Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE. DSD Fernando Herrera, Hector Posadas, Eugenio Villar, Daniel Calvo
2012	Misc	`conf`	Evaluation of High Performance Clusters in Private Cloud Computing Environments. DCAI Julio Gómez López, Eugenio Villar, Gabriel Molero, Alejandro Cama-Pinto
2012	—	`conf`	Model-Driven Methodology for the Development of Multi-level Executable Environments. FDL (Selected Papers) Fernando Herrera, Pablo Peñil, Hector Posadas, Eugenio Villar
2012	—	`conf`	The COMPLEX Eclipse framework for UML/MARTE specification and design space exploration of embedded systems. DASIP Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia
2012	J	`jnl`	Towards automated implementation of adaptive systems from abstract SystemC specifications - From SystemC adaptive processes to embedded software and to synthesizable hardware descriptions. Des. Autom. Embed. Syst. Fernando Herrera, Íñigo Ugarte, Eugenio Villar
2011	J	`jnl`	A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design. J. Low Power Electron. Daniel Calvo, Pablo González, Luis Diaz, Hector Posadas, Pablo Sánchez, Eugenio Villar, Andrea Acquaviva, Enrico Macii
2011	C	`conf`	A framework for the generation from UML/MARTE models of IPXACT HW platform descriptions for multi-level performance estimation. FDL Fernando Herrera, Eugenio Villar
2011	J	`jnl`	Early, time-approximate modeling of multi-OS. linux platforms in a systemC co-simulation environment. Comput. Syst. Sci. Eng. Hector Posadas, Eugenio Villar, Dominique Ragot, Marcos Martínez
2011	—	`conf`	Fast data-cache modeling for native co-simulation. ASP-DAC Hector Posadas, Luis Diaz, Eugenio Villar
2011	—	`ch.`	High-level modeling and exploration of a powerline communication network based on System-on-Chip. Multi-objective Design Space Exploration of Multiprocessor SoC Architectures Marcos Martínez, David Ferruz, Hector Posadas, Eugenio Villar
2011	—	`ch.`	M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration. Multi-objective Design Space Exploration of Multiprocessor SoC Architectures Hector Posadas, Sara Real, Eugenio Villar
2011	—	`book`	Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, The MULTICUBE Approach. Cristina Silvano, William Fornaciari, Eugenio Villar
2011	C	`conf`	Systemc refinement of abstract adaptive processes for implementation into Dynamically Reconfigurable Hardware. FDL Fernando Herrera, Eugenio Villar, Philipp A. Hartmann
2011	—	`ch.`	The MULTICUBE Design Flow. Multi-objective Design Space Exploration of Multiprocessor SoC Architectures Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Fan Dongrui, Hao Zhang
2010	B	`conf`	AADS+: AADL Simulation Including the Behavioral Annex. ICECCS Roberto Varona-Gomez, Eugenio Villar
2010	C	`conf`	Early Modeling of Linux-Based RTOS Platforms in a SystemC Time-Approximate Co-simulation Environment. ISORC Hector Posadas, Eugenio Villar, Dominique Ragot, Marcos Martínez
2010	—	`conf`	Fast instruction cache modeling for approximate timed HW/SW co-simulation. ACM Great Lakes Symposium on VLSI Juan Castillo, Hector Posadas, Eugenio Villar, Marcos Martínez
2010	C	`conf`	Formal Foundations for MARTE-SystemC Interoperability. FDL Pablo Peñil, Fernando Herrera, Eugenio Villar
2010	B	`conf`	Formal Modeling for UML/MARTE Concurrency Resources. ICECCS Pablo Peñil, Hector Posadas, Eugenio Villar
2010	C	`conf`	Formal Support for Untimed SystemC Specifications: Application to High-level Synthesis. FDL Eugenio Villar, Fernando Herrera, Víctor Fernández
2010	J	`jnl`	Generating heterogeneous executable specifications in SystemC from UML/MARTE models. Innov. Syst. Softw. Eng. Pablo Peñil, Julio L. Medina, Hector Posadas, Eugenio Villar
2010	—	`conf`	L2 Cache Modeling based on address modification for Native Co-Simulation in SystemC. SIES Sara Real, Hector Posadas, Eugenio Villar
2010	—	`conf`	MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures. ISVLSI (Selected papers) Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Dongrui Fan, Hao Zhang, Shibin Tang
2010	—	`conf`	MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures. ISVLSI Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Dongrui Fan, Hao Zhang, Shibin Tang
2010	—	`conf`	Modeling Separate Memory Spaces in Native Co-simulation with SystemC for Design Space Exploration. ARCS Workshops Hector Posadas, Eugenio Villar
2010	—	`conf`	The SATURN Approach to SysML-Based HW/SW Codesign. ISVLSI (Selected papers) Wolfgang Müller, Da He, Fabian Mischkalla, Arthur Wegele, Adrian Larkham, Paul Whiston, Pablo Peñil, Eugenio Villar, Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda
2010	—	`conf`	The SATURN Approach to SysML-Based HW/SW Codesign. ISVLSI Wolfgang Müller, Da He, Fabian Mischkalla, Arthur Wegele, Paul Whiston, Pablo Peñil, Eugenio Villar, Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda
2009	B	`conf`	AADL Simulation and Performance Analysis in SystemC. ICECCS Roberto Varona-Gomez, Eugenio Villar
2009	—	`conf`	Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation. IESS Hector Posadas, Eugenio Villar
2009	C	`conf`	Local application of simulation directed for Exhaustive Coverage of Schedulings of SystemC specifications. FDL Fernando Herrera, Eugenio Villar
2008	J	`jnl`	Bridging MoCs in SystemC Specifications of Heterogeneous Systems. EURASIP J. Embed. Syst. Markus Damm, Jan Haase, Christoph Grimm, Fernando Herrera, Eugenio Villar
2008	J	`jnl`	C-Based Design of Heterogeneous Embedded Systems. EURASIP J. Embed. Syst. Christoph Grimm, Axel Jantsch, Sandeep Kumar Shukla, Eugenio Villar
2008	A	`conf`	Heterogeneous System-level Specification Using SystemC. DATE Eugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel
2008	C	`conf`	Specification of Adaptive HW/SW Systems in SystemC. FDL Fernando Herrera, Eugenio Villar, Philipp A. Hartmann
2007	J	`jnl`	A framework for heterogeneous specification and design of electronic embedded systems in SystemC. ACM Trans. Design Autom. Electr. Syst. Fernando Herrera, Eugenio Villar
2007	C	`conf`	A general approach to the interoperability of HetSC and SystemC-AMS. FDL Fernando Herrera, Eugenio Villar, Christoph Grimm, Markus Damm, Jan Haase
2007	C	`conf`	Protocol Bus Modeling using inheritance with TLM2.0. FDL Hector Posadas, David Quijano, Eugenio Villar, Marcos Martínez
2007	—	`conf`	Specification for SystemC-AADL interoperability. WISES Eduardo de las Heras, Eugenio Villar
2007	B	`conf`	The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. FPL Andreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm, Markus Damm, Jan Haase, Florian Brame, Fernando Herrera, Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, Marcos Martínez
2006	A*	`conf`	A framework for embedded system specification under different models of computation in SystemC. DAC Fernando Herrera, Eugenio Villar
2006	C	`conf`	Extension of the SystemC Kernel for Simulation Coverage. FDL Fernando Herrera, Eugenio Villar
2006	—	`conf`	POSIX modeling in SystemC. ASP-DAC Hector Posadas, Jesús Ádamez, Pablo Sánchez, Eugenio Villar, Francisco Blasco
2005	C	`conf`	Mixing Synchronous Reactive and Untimed Models of Computation. FDL Fernando Herrera, Eugenio Villar
2005	J	`jnl`	RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model. Des. Autom. Embed. Syst. Hector Posadas, Jesús Ádamez, Eugenio Villar, Francisco Blasco, F. Escuder
2004	C	`conf`	Heterogeneous System-Level Specification in SystemC. FDL Fernando Herrera, Pablo Sánchez, Eugenio Villar
2004	J	`jnl`	Single Source Design Environment for Embedded Systems Based on SystemC. Des. Autom. Embed. Syst. Hector Posadas, Fernando Herrera, Víctor Fernández, Pablo Sánchez, Eugenio Villar, Francisco Blasco
2004	A	`conf`	System-Level Performance Analysis in SystemC. DATE Hector Posadas, Fernando Herrera, Pablo Sánchez, Eugenio Villar, Francisco Blasco
2003	C	`conf`	Modeling of CSP, KPN and SR Systems with SystemC. FDL Fernando Herrera, Pablo Sánchez, Eugenio Villar
2003	—	`ch.`	Systematic Embedded Software Generation from Systemc. Embedded Software for SoC Fernando Herrera, Héctor Posadas, Pablo Sánchez, Eugenio Villar
2003	A	`conf`	Systemic Embedded Software Generation from SystemC. DATE Fernando Herrera, Hector Posadas, Pablo Sánchez, Eugenio Villar
2001	A	`conf`	C/C++: progress or deadlock in system-level specification. DATE Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, Jonas Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong
2000	J	`jnl`	System Specification Experiments on a Common Benchmark. IEEE Des. Test Comput. Giulio Gorla, Eduard Moser, Wolfgang Nebel, Eugenio Villar
1999	Misc	`conf`	Hardware/Software Embedded System Specifiaction and Design Using Ada and VHDL. Ada-Europe Adrian López, Maite Veiga, Eugenio Villar
1998	J	`jnl`	An algorithm for clock cycle selection in behavioral synthesis. J. Syst. Archit. Pedro Tabuenca, Pablo Sánchez, Eugenio Villar
1996	J	`jnl`	ASPDAC 1995: HDL synthesizability and interoperability. IEEE Des. Test Comput. Masaharu Imai, Eugenio Villar
1996	J	`jnl`	VHDL synthesis description portability: The need for Level synthesis subsets. J. Syst. Archit. Manfred Selz, Wolfgang Ecker, Eugenio Villar
1995	—	`conf`	Future direction of synthesizability and interoperability of HDL's: part 1. ASP-DAC Masaharu Imai, Eugenio Villar
1995	—	`conf`	Future direction of synthesizabilty and interoperability of HDL's: part 2. ASP-DAC Eugenio Villar, Masaharu Imai
1992	J	`jnl`	ESP, a structure synthesis program. Microprocess. Microprogramming E. Randon, P. Sanchez, Eugenio Villar