Eugene Koskin - RankMe

22 papers A* 1B 1C 6Journal 7Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A 0.012mm ISCAS Ali Esmailiyan, Teerachot Siriburanon, Dennis Andrade-Miceli, Eugene Koskin, Dirk Leipold, David J. Redmond, Imran Bashir, Elena Blokhina, Robert Bogdan Staszewski
2025	C	`conf`	A Ring Temperature Sensor for Quantum Applications. ISCAS Ali Esmailiyan, Eugene Koskin, Dennis Andrade-Miceli, Andrii Sokolov, Teerachot Siriburanon, Dirk Leipold, David J. Redmond, Imran Bashir, Elena Blokhina, Robert Bogdan Staszewski
2024	J	`jnl`	Gate-Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms. CoRR Dmytro Mishagli, Eugene Koskin, Elena Blokhina
2024	A*	`conf`	Quantum Theory and Application of Contextual Optimal Transport. ICML Nicola Mariella, Albert Akhriev, Francesco Tacchino, Christa Zoufal, Juan Carlos Gonzalez-Espitia, Benedek Harsanyi, Eugene Koskin, Ivano Tavernelli, Stefan Woerner, Marianna Rapsomaniki, Sergiy Zhuk, Jannis Born
2024	J	`jnl`	Quantum Theory and Application of Contextual Optimal Transport. CoRR Nicola Mariella, Albert Akhriev, Francesco Tacchino, Christa Zoufal, Juan Carlos Gonzalez-Espitia, Benedek Harsanyi, Eugene Koskin, Ivano Tavernelli, Stefan Woerner, Marianna Rapsomaniki, Sergiy Zhuk, Jannis Born
2023	J	`jnl`	An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS. IEEE Trans. Circuits Syst. II Express Briefs Ali Esmailiyan, Elena Blokhina, Dennis Andrade-Miceli, Eoin Faust, Panagiotis Giounanlis, Dirk Leipold, Hongying Wang, Imran Bashir, Eugene Koskin, Teerachot Siriburanon, Robert Bogdan Staszewski
2021	J	`jnl`	All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance. IEEE Trans. Circuits Syst. I Regul. Pap. Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina
2021	J	`jnl`	Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model. IEEE Trans. Circuits Syst. II Express Briefs Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina
2020	—	`conf`	Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process. ECCTD Pierre Bisiaux, Elena Blokhina, Eugene Koskin, Teerachot Siriburanon, Dimitri Galayko
2020	C	`conf`	Electrostatic Control and Entanglement of CMOS Position-Based Qubits. ISCAS Panagiotis Giounanlis, Andrii Sokolov, Elena Blokhina, Eugene Koskin, Imran Bashir, Dirk Leipold, Robert Bogdan Staszewski
2020	—	`conf`	FPGA Validation of Event-Driven ADPLL. ECCTD Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina
2020	—	`conf`	Simulation Methodology for Electron Transfer in CMOS Quantum Dots. ICCS (6) Andrii Sokolov, Dmytro Mishagli, Panagiotis Giounanlis, Imran Bashir, Dirk Leipold, Eugene Koskin, Robert Bogdan Staszewski, Elena Blokhina
2020	—	`conf`	Synchronisation in Noisy PLL Networks: Time Domain Model and its Analysis. ECCTD Eugene Koskin, Maksim Balakin, Nikita M. Ryskin, Dimitri Galayko, Elena Blokhina
2019	—	`conf`	All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping. NEWCAS Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina
2019	C	`conf`	Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation. ISCAS Dmytro Mishagli, Eugene Koskin, Elena Blokhina
2018	J	`jnl`	A Concept of Synchronous ADPLL Networks in Application to Small-Scale Antenna Arrays. IEEE Access Eugene Koskin, Dimitri Galayko, Elena Blokhina
2018	C	`conf`	Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs. ISCAS Eugene Koskin, Dimitri Galayko, Elena Blokhina
2018	J	`jnl`	Generation of a Clocking Signal in Synchronized All-Digital PLL Networks. IEEE Trans. Circuits Syst. II Express Briefs Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina
2017	C	`conf`	Semianalytical model for high speed analysis of all-digital PLL clock-generating networks. ISCAS Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina
2016	—	`conf`	Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks. NEWCAS Eugene Koskin, Elena Blokhina, Chuan Shan, Eldar Zianbetov, Orla Feely, Dimitri Galayko
2016	—	`conf`	Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks. ICECS Eugene Koskin
2015	B	`conf`	Mode-locking in a network of kuramoto-like oscillators. IJCNN Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina