Eslam Yahya

21 papers B 1C 4Journal 3Unranked 13
YearRankTypeTitle / Venue / Authors
2018 J jnl
A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shady O. Agwa, Eslam Yahya, Yehea Ismail
2017 C conf
130nm Low power asynchronous AES core.
ISCAS
Nada El-meligy, Moustafa Amin, Eslam Yahya, Yehea Ismail
2017 C conf
Power efficient AES core for IoT constrained devices implemented in 130nm CMOS.
ISCAS
Shady O. Agwa, Eslam Yahya, Yehea Ismail
2016 C conf
Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis.
ISCAS
Tarek Ramadan, Eslam Yahya, Mohamed Dessouky, Yehea Ismail
2016 J jnl
ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing.
IEEE Trans. Circuits Syst. II Express Briefs
Shady O. Agwa, Eslam Yahya, Yehea Ismail
2016 — conf
Presenting a synchronous - Asynchronous standard cell library based on 7nm FinFET technology.
ICM
Eslam Amr, Marina Maher, Amir Rashad, Mohamed Raafat, Yosif Diaa, Eslam Yahya, Yehea Ismail
2015 — conf
Coupling capacitance extraction in through-silicon via (TSV) arrays.
ICECS
Tarek Ramadan, Eslam Yahya, Mohamed Dessouky, Yehea I. Ismail
2015 — conf
Deadlock detection in conditional asynchronous circuits under mismatched branch selection.
ICECS
Eslam Yahya, Hatem M. Zakaria, Yehea Ismail
2015 — conf
Different scenarios for estimating coupling capacitances of through silicon via (TSV) arrays.
ICEAC
Kareem Ali, Eslam Yahya, Alaa B. El-Rouby, Yehea Ismail
2015 J jnl
Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays.
Microelectron. J.
Karim Ali, Eslam Yahya, Alaa B. El-Rouby, Yehea I. Ismail
2013 — conf
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation.
ASYNC
Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin
2013 — conf
Variability mitigation using correction function technique.
ICECS
Shady O. Agwa, Eslam Yahya, Yehea I. Ismail
2010 C conf
A high-speed high-resolution low-phase noise oscillator using self-timed rings.
VLSI-SoC
Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet
2010 — conf
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case.
PATMOS
Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet
2010 — conf
Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks.
VLSI-SoC (Selected Papers)
Oussama Elissati, Sébastien Rieubon, Eslam Yahya, Laurent Fesquet
2009 — conf
Asynchronous design: A promising paradigm for electronic circuits and systems.
ICECS
Eslam Yahya, Laurent Fesquet
2009 — conf
Programmable/Stoppable Oscillator Based on Self-Timed Rings.
ASYNC
Eslam Yahya, Oussama Elissati, Hatem M. Zakaria, Laurent Fesquet, Marc Renaudin
2008 — conf
Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm.
ICECS
Eslam Yahya, Marc Renaudin
2007 — conf
Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays.
ICECS
Eslam Yahya, Marc Renaudin
2006 — conf
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis.
PATMOS
Eslam Yahya, Marc Renaudin
2003 B conf
Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA.
FPL
François Charot, Eslam Yahya, Charles Wagner