Ernest S. Kuh - RankMe

83 papers A* 18A 14B 2C 1Misc 2Journal 24Unranked 22

Year	Rank	Type	Title / Venue / Authors
2011	—	`conf`	Professor Ernest Kuh's talk. ISPD Ernest S. Kuh
2009	—	`conf`	Design methodology of high performance on-chip global interconnect using terminated transmission-line. ISQED Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
2009	—	`conf`	High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng
2008	A	`conf`	Efficient and accurate eye diagram prediction for high speed signaling. ICCAD Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ernest S. Kuh
2008	—	`conf`	Low Power Passive Equalizer Design for Computer Memory Links. Hot Interconnects Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
2008	A*	`conf`	Low power passive equalizer optimization using tritonic step response. DAC Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng
2007	J	`jnl`	Two-Stage Newton-Raphson Method for Transistor-Level Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhengyong Zhu, He Peng, Chung-Kuan Cheng, Khosro Rouz, Manjit Borah, Ernest S. Kuh
2006	—	`conf`	An unconditional stable general operator splitting method for transistor level transient analysis. ASP-DAC Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh
2005	—	`conf`	Efficient transient simulation for transistor-level analysis. ASP-DAC Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh
2002	—	`conf`	Accurate reduced RL model for frequency dependent transmission lines. ICECS Qingjian Yu, Ernest S. Kuh
2001	A	`conf`	Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements. DATE Qingjian Yu, Ernest S. Kuh
2001	J	`jnl`	Moment computation of lumped and distributed coupled RC trees with application to delay and crosstalk estimation. Proc. IEEE Qingjian Yu, Ernest S. Kuh
2001	—	`conf`	New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees. ISQED Qingjian Yu, Ernest S. Kuh
2000	A*	`conf`	Floorplan sizing by linear programming approximation. DAC Pinghong Chen, Ernest S. Kuh
2000	A*	`conf`	Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks. DAC Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh
1999	A	`conf`	Coupled Noise Estimation for Distributed RC Interconnect Model. DATE Janet Meiling Wang, Qingjian Yu, Ernest S. Kuh
1999	A	`conf`	The Chebyshev expansion based passive model for distributed interconnect networks. ICCAD Janet Meiling Wang, Ernest S. Kuh, Qingjian Yu
1998	A	`conf`	A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction. DATE Dongsheng Wang, Ernest S. Kuh
1998	—	`conf`	A new general connectivity model and its applications to timing-driven Steiner tree routing. ICECS Dongsheng Wang, Ernest S. Kuh
1998	A	`conf`	Multipoint moment matching model for multiport distributed interconnect networks. ICCAD Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh
1998	—	`conf`	Sequence-pair based placement method for hard/soft/pre-placed modules. ISPD Hiroshi Murata, Ernest S. Kuh
1997	J	`jnl`	A performance-driven IC/MCM placement algorithm featuring explicit design space exploration. ACM Trans. Design Autom. Electr. Syst. Henrik Esbensen, Ernest S. Kuh
1997	J	`jnl`	Combining Technology Mapping With Layout. VLSI Design Massoud Pedram, Narasimha B. Bhat, Ernest S. Kuh
1997	—	`conf`	Physical design: reminiscing and looking ahead. ISPD Ernest S. Kuh
1997	J	`jnl`	Post global routing crosstalk synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tianxiong Xue, Ernest S. Kuh, Dongsheng Wang
1997	Misc	`conf`	SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits. VLSI Design Premal Buch, Ernest S. Kuh
1997	J	`jnl`	TIGER: an efficient timing-driven global router for gate array and standard cell layout design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
1996	—	`conf`	EXPLORER: an interactive floorplanner for design space exploration. EURO-DAC Henrik Esbensen, Ernest S. Kuh
1996	J	`jnl`	Moment models of general transmission lines with application to interconnect analysis and optimization. IEEE Trans. Very Large Scale Integr. Syst. Qingjian Yu, Ernest S. Kuh, Tianxiong Xue
1996	—	`conf`	Performance-Driven Interconnect Global Routing. Great Lakes Symposium on VLSI Dongsheng Wang, Ernest S. Kuh
1996	A	`conf`	Post global routing crosstalk risk estimation and reduction. ICCAD Tianxiong Xue, Ernest S. Kuh, Dongsheng Wang
1996	A	`conf`	Simulation and sensitivity analysis of transmission line circuits by the characteristics method. ICCAD Jun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh
1995	J	`jnl`	Exact moment matching model of transmission lines and application to interconnect delay estimation. IEEE Trans. Very Large Scale Integr. Syst. Qingjian Yu, Ernest S. Kuh
1995	J	`jnl`	Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Akira Onozawa, Kamal Chaudhary, Ernest S. Kuh
1995	A	`conf`	Post routing performance optimization via multi-link insertion and non-uniform wiresizing. ICCAD Tianxiong Xue, Ernest S. Kuh
1995	—	`conf`	Post routing performance optimization via tapered link insertion and wiresizing. EURO-DAC Tianxiong Xue, Ernest S. Kuh
1995	—	`conf`	Techniques for fast circuit simulation applied to power estimation of CMOS circuits. ISLPD Premal Buch, Shen Lin, Vijay Nagasamy, Ernest S. Kuh
1993	—	`conf`	A new performance-driven global routing algorithm for gate array. VLSI Tianxiong Xue, Takashi Fujii, Ernest S. Kuh
1993	A	`conf`	A spacing algorithm for performance enhancement and cross-talk reduction. ICCAD Kamal Chaudhary, Akira Onozawa, Ernest S. Kuh
1993	A*	`conf`	An Efficient Timing-Driven Global Routing Algorithm. DAC Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh
1993	—	`conf`	Circuit simulation for large interconnected IC networks. VLSI Shen Lin, Ernest S. Kuh
1993	A*	`conf`	Performance-Driven Steiner Tree Algorithm for Global Routing. DAC Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang
1993	A*	`conf`	Quadratic Boolean Programming for Performance-Driven System Partitioning. DAC Minshine Shih, Ernest S. Kuh
1993	J	`jnl`	Stepwise equivalent conductance circuit simulation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska
1992	Misc	`conf`	A New Accurate and Efficient Timing Simulator. VLSI Design Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska
1992	A*	`conf`	FARM: An Efficient Feed-Through Pin Assignment Algorithm. DAC Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
1992	A*	`conf`	Performance-Driven System Partitioning on Multi-Chip Modules. DAC Minshine Shih, Ernest S. Kuh, Ren-Song Tsay
1992	A*	`conf`	Power and Ground Network Topology Optimization for Cell Based VLSIs. DAC Takashi Mitsuhashi, Ernest S. Kuh
1992	A*	`conf`	Transient Simulation of Lossy Interconnect. DAC Shen Lin, Ernest S. Kuh
1992	—	`conf`	Transient simulation of lossy coupled transmission lines. EURO-DAC Shen Lin, Ernest S. Kuh
1991	C	`conf`	I/O Pad Assignment Based on the Circuit Structure. ICCD Massoud Pedram, Kamal Chaudhary, Ernest S. Kuh
1991	J	`jnl`	New Algorithms For Two- and Three-Layer Channel Routin. Int. J. Circuit Theory Appl. Deborah C. Wang, Ernest S. Kuh
1991	A	`conf`	RITUAL: Performance Driven Placement Algorithm for Small Cell ICs. ICCAD Arvind Srinivasan, Kamal Chaudhary, Ernest S. Kuh
1991	—	`conf`	SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits. EURO-DAC Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh
1990	A	`conf`	A Fast Algorithm for Performance-Driven Placement. ICCAD Michael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh
1990	J	`jnl`	A Simulation-Based Method for Generating Tests for Sequential Circuits. IEEE Trans. Computers Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh
1990	A*	`conf`	Clock Routing for High-Performance ICs. DAC Michael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh
1990	A*	`conf`	Delay and Area Optimization in Standard-Cell Design. DAC Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh
1990	A	`conf`	Floorplanning with Pin Assignment. ICCAD Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh
1990	J	`jnl`	Geometric approach to VLSI layout compaction. Int. J. Circuit Theory Appl. Xiao-Ming Xiong, Ernest S. Kuh
1990	—	`conf`	MOLE: a sea-of-gates detailed router. EURO-DAC Arvind Srinivasan, Ernest S. Kuh
1990	J	`jnl`	Recent advances in VLSI layout. Proc. IEEE Ernest S. Kuh, Tatsuo Ohtsuki
1989	A*	`conf`	Performance-driven Placement of Cell Based IC's. DAC Michael A. B. Jackson, Ernest S. Kuh
1988	—	`conf`	A sequential circuit test generation using threshold-value simulation. FTCS Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh
1988	A	`conf`	Hierarchical placement for macrocells: a 'meet in the middle' approach. ICCAD Bernhard Eschermann, Wayne Wei-Ming Dai, Ernest S. Kuh, Massoud Pedram
1988	J	`jnl`	PROUD: a sea-of-gates placement algorithm. IEEE Des. Test Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
1988	A*	`conf`	Proud: A Fast Sea-of-Gates Placement Algorithm. DAC Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
1988	A*	`conf`	The Constrained Via Minimization Problem for PCB and VLSI Design. DAC Xiao-Ming Xiong, Ernest S. Kuh
1987	A*	`conf`	A Dynamic and Efficient Representation of Building-Block Layout. DAC Wayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh
1987	A*	`conf`	Nutcracker: An Efficient and Intelligent Channel Spacer. DAC Xiao-Ming Xiong, Ernest S. Kuh
1987	J	`jnl`	Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wayne Wei-Ming Dai, Ernest S. Kuh
1986	J	`jnl`	Glitter: A Gridless Variable-Width Channel Router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Howard H. Chen, Ernest S. Kuh
1985	J	`jnl`	Routing Region Definition and Ordering Scheme for Building-Block Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wayne Wei-Ming Dai, Tetsuo Asano, Ernest S. Kuh
1984	J	`jnl`	An Efficient Single-Row Routing Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh
1984	J	`jnl`	Module Placement Based on Resistive Network Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Kuan Cheng, Ernest S. Kuh
1983	J	`jnl`	Editorial: Routing in Microelectronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ernest S. Kuh
1983	J	`jnl`	On the Layering Problem of Multilayer PWB Wiring. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
1982	J	`jnl`	Double-row planar routing and permutation layout. Networks Shuji Tsukiyama, Ernest S. Kuh
1982	J	`jnl`	Efficient Algorithms for Channel Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Takeshi Yoshimura, Ernest S. Kuh
1981	A*	`conf`	On the layering problem of multilayer PWB wiring. DAC Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
1980	—	`conf`	On the layering problem of multilayer PWB wiring. Graph Theory and Algorithms Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
1979	B	`conf`	One-dimensional logic gate assignment and interval graphs. COMPSAC Tatsuo Ohtsuki, Hajimu Mori, Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa
1979	B	`conf`	Single-row routing and extensions. COMPSAC Ernest S. Kuh