Eriko Nurvitadhi

82 papers A* 2A 14B 9C 1Misc 10Journal 27Unranked 18

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	FLASH: Fast All-to-All Communication in GPU Clusters. CoRR Yiran Lei, Dongjoo Lee, Liangyu Zhao, Daniar Kurniawan, Chanmyeong Kim, Heetaek Jeong, Changsu Kim, Hyeonseong Choi, Liangcheng Yu, Arvind Krishnamurthy, Justine Sherry, Eriko Nurvitadhi
2025	J	`jnl`	MangoBoost Alice: Extremely Fast, Seamless, and Versatile FPGA-Accelerated DPU Solutions. IEEE Micro Heetaek Jeong, Wonsik Lee, Eunjin Baek, Changsu Kim, Changyeon Jo, Dongju Chae, Kanghyun Choi, Hamin Jang, Mohamed A. Elgammal, Sungmin Hong, Eriko Nurvitadhi, Dongup Kwon, Jangwoo Kim
2024	J	`jnl`	High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. ACM Trans. Reconfigurable Technol. Syst. Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2023	J	`jnl`	A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks. ACM Trans. Archit. Code Optim. Suyeon Hur, Seongmin Na, Dongup Kwon, Joonsung Kim, Andrew Boutros, Eriko Nurvitadhi, Jangwoo Kim
2023	J	`jnl`	Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA. IEEE Trans. Computers Zhipeng Zhao, Joseph Melber, Siddharth Sahay, Shashank Obla, Eriko Nurvitadhi, James C. Hoe
2023	J	`jnl`	RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. CoRR Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
2023	J	`jnl`	Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk
2022	J	`jnl`	Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices. IEEE Access Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
2022	J	`jnl`	FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems. IEEE Comput. Archit. Lett. Rui Ma, Evangelos Georganas, Alexander Heinecke, Sergey Gribok, Andrew Boutros, Eriko Nurvitadhi
2022	J	`jnl`	FPGA-based AI Smart NICs for Scalable Distributed AI Training Systems. CoRR Rui Ma, Evangelos Georganas, Alexander Heinecke, Andrew Boutros, Eriko Nurvitadhi
2022	—	`conf`	HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming. ASAP Adel Ejjeh, Leon Medvinsky, Aaron Councilman, Hemang Nehra, Suraj Sharma, Vikram S. Adve, Luigi Nardi, Eriko Nurvitadhi, Rob A. Rutenbar
2022	B	`conf`	RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. FPL Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
2022	J	`jnl`	Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk
2022	J	`jnl`	Stratix 10 NX Architecture. ACM Trans. Reconfigurable Technol. Syst. Martin Langhammer, Eriko Nurvitadhi, Sergey Gribok, Bogdan Pasca
2021	—	`conf`	Cache Compression with Efficient in-SRAM Data Comparison. NAS Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi R. Iyer, Li Zhao, Reetuparna Das
2021	Misc	`conf`	Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das
2021	B	`conf`	DO-GPU: Domain Optimizable Soft GPUs. FPL Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, Rajesh Vivekanandham, Aravind Dasu, Martin Langhammer, Derek Chiou
2021	B	`conf`	End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2021	J	`jnl`	Enhancing High-Level Synthesis Using a Meta-Programming Approach. IEEE Trans. Computers Jessica Vandebon, José Gabriel de Figueiredo Coutinho, Wayne Luk, Eriko Nurvitadhi
2021	J	`jnl`	FlexScore: Quantifying Flexibility. IEEE Comput. Archit. Lett. Tian Tan, Eriko Nurvitadhi, Aravind Dasu, Martin Langhammer, Derek Chiou
2021	J	`jnl`	Specializing FGPU for Persistent Deep Learning. ACM Trans. Reconfigurable Technol. Syst. Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu, Derek Chiou
2021	—	`conf`	Specializing for Efficiency: Customizing AI Inference Processors on FPGAs. ICM Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
2021	A	`conf`	Stratix 10 NX Architecture and Applications. FPGA Martin Langhammer, Eriko Nurvitadhi, Bogdan Pasca, Sergey Gribok
2020	—	`conf`	A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. FPT Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk
2020	Misc	`conf`	Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies. FCCM Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Tim Todman
2020	—	`conf`	Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs. FPT Andrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz, Martin Langhammer
2020	A	`conf`	FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. ICCAD Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2020	Misc	`conf`	Optimizing Reconfigurable Recurrent Neural Networks. FCCM Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk
2020	—	`conf`	SLATE: Managing Heterogeneous Cloud Functions. ASAP Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik
2020	A*	`conf`	Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels. DAC Dongup Kwon, Suyeon Hur, Hamin Jang, Eriko Nurvitadhi, Jangwoo Kim
2019	B	`conf`	Automatic Compiler Based FPGA Accelerator for CNN Training. FPL Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2019	J	`jnl`	Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2019	J	`jnl`	Dark Wires and the Opportunities for Reconfigurable Logic. IEEE Comput. Archit. Lett. Tian Tan, Eriko Nurvitadhi, Derek Chiou
2019	—	`conf`	Enhanced Heterogeneous Cloud: Transparent Acceleration and Elasticity. FPT Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik
2019	A	`conf`	Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. FPGA Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu
2019	—	`conf`	FPGA-based Computing in the Era of AI and Big Data. ISPD Eriko Nurvitadhi
2019	Misc	`conf`	Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform. FCCM Yu Wang, James C. Hoe, Eriko Nurvitadhi
2019	—	`conf`	Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs. FPT Eriko Nurvitadhi, Mishali Naik, Andrew Boutros, Prerna Budhkar, Ali Jafari, Dongup Kwon, David Sheffield, Abirami Prabhakaran, Karthik Gururaj, Pranavi Appana
2019	B	`conf`	Specializing FGPU for Persistent Deep Learning. FPL Rui Ma, Derek Chiou, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu
2019	Misc	`conf`	Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. FCCM Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu
2018	A	`conf`	A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. FPGA Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
2018	—	`conf`	Evaluating The Highly-Pipelined Intel Stratix 10 FPGA Architecture Using Open-Source Benchmarks. FPT Tian Tan, Eriko Nurvitadhi, David Shih, Derek Chiou
2018	J	`jnl`	Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. CoRR Philip Colangelo, Nasibeh Nasiri, Asit K. Mishra, Eriko Nurvitadhi, Martin Margala, Kevin Nealis
2018	Misc	`conf`	Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. FCCM Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
2018	A	`conf`	Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). FPGA Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
2018	A	`conf`	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu
2018	B	`conf`	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev
2018	—	`conf`	WRPN: Wide Reduced-Precision Networks. ICLR (Poster) Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
2017	Misc	`conf`	Accelerating Deep Convolutional Networks using low-precision and sparsity. ICASSP Ganesh Venkatesh, Eriko Nurvitadhi, Debbie Marr
2017	A	`conf`	Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? FPGA Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Ong Gee Hock, Yeong Tat Liew, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra, Guy Boudoukh
2017	—	`conf`	Customizable FPGA OpenCL matrix multiply design template for deep neural networks. FPT Jack Yinger, Eriko Nurvitadhi, Davor Capalija, Andrew C. Ling, Debbie Marr, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra
2017	—	`conf`	Fine-grained accelerators for sparse machine learning workloads. ASP-DAC Asit K. Mishra, Eriko Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, Debbie Marr
2017	B	`conf`	High performance binary neural networks on the Xeon+FPGA™ platform. FPL Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
2017	J	`jnl`	WRPN: Training and Inference using Wide Reduced-Precision Networks. CoRR Asit K. Mishra, Jeffrey J. Cook, Eriko Nurvitadhi, Debbie Marr
2017	J	`jnl`	WRPN: Wide Reduced-Precision Networks. CoRR Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
2016	—	`ch.`	3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. Large-Scale Visual Geo-Localization Hyun Soo Park, Yu Wang, Eriko Nurvitadhi, James C. Hoe, Yaser Sheikh, Mei Chen
2016	A	`conf`	A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems. FPGA Gabriel Weisz, Joseph Melber, Yu Wang, Kermin Fleming, Eriko Nurvitadhi, James C. Hoe
2016	—	`conf`	Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC. FPT Eriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit K. Mishra, Ganesh Venkatesh, Debbie Marr
2016	J	`jnl`	Accelerating Deep Convolutional Networks using low-precision and sparsity. CoRR Ganesh Venkatesh, Eriko Nurvitadhi, Debbie Marr
2016	B	`conf`	Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. FPL Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr
2016	A	`conf`	Hardware accelerator for analytics of sparse data. DATE Eriko Nurvitadhi, Asit K. Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr
2015	Misc	`conf`	A sparse matrix vector multiply accelerator for support vector machine. CASES Eriko Nurvitadhi, Asit K. Mishra, Debbie Marr
2015	B	`conf`	Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. FPL Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, José F. Martínez, Rob A. Rutenbar
2014	Misc	`conf`	GraphGen: An FPGA Framework for Vertex-Centric Graph Computation. FCCM Eriko Nurvitadhi, Gabriel Weisz, Yu Wang, Skand Hurkat, Marie Nguyen, James C. Hoe, José F. Martínez, Carlos Guestrin
2014	—	`conf`	Programmable Automotive Headlights. ECCV (4) Robert Tamburo, Eriko Nurvitadhi, Abhishek Chugh, Mei Chen, Anthony Rowe, Takeo Kanade, Srinivasa G. Narasimhan
2013	—	`conf`	3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. CVPR Workshops Hyun Soo Park, Yu Wang, Eriko Nurvitadhi, James C. Hoe, Yaser Sheikh, Mei Chen
2013	Misc	`conf`	Hardware-efficient stereo estimation using a residual-based approach. ICASSP Abhishek A. Sharma, Kaustubh Neelathalli, Diana Marculescu, Eriko Nurvitadhi
2013	C	`conf`	MEMOCODE 2013 hardware/software co-design contest: Stereo matching. MEMOCODE Eriko Nurvitadhi
2011	J	`jnl`	Automatic Pipelining From Transactional Datapath Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
2011	—	`conf`	Integrating formal verification and high-level processor pipeline synthesis. SASP Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
2010	A*	`conf`	Automatic multithreaded pipeline synthesis from transactional datapath specifications. DAC Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam
2010	A	`conf`	Automatic pipelining from transactional datapath specifications. DATE Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
2009	J	`jnl`	ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. ACM Trans. Reconfigurable Technol. Syst. Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi
2008	A	`conf`	A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. FPGA Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
2008	J	`jnl`	Active Cache Emulator. IEEE Trans. Very Large Scale Integr. Syst. Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu
2007	J	`jnl`	Adaptive semi-soft handoff for Cellular IP networks. Int. J. Wirel. Mob. Comput. Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Kim
2007	A	`conf`	PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. IPDPS Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
2006	A	`conf`	Design, implementation, and verification of active cache emulator (ACE). FPGA Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu
2005	A	`conf`	Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. ICS Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu
2005	J	`jnl`	Dynamic voltage scaling techniques for power efficient video decoding. J. Syst. Archit. Ben Lee, Eriko Nurvitadhi, Reshma Dixit, Chansu Yu, Myungchul Kim
2005	J	`jnl`	TRUSS: A Reliable, Scalable Server Architecture. IEEE Micro Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
2003	—	`conf`	A Comparative Study of Dynamic Voltage Scaling Techniques for Low-Power Video Decoding. Embedded Systems and Applications Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Kim