Erik Jan Marinissen

189 papers A* 2A 57B 25C 3Misc 7Journal 56Unranked 38

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Chiplet Interconnect Repair for Clustered Defects with Minimal Propagation Delay. ATS Po-Yao Chuang, Erik Jan Marinissen
2025	A	`conf`	Chiplet Interconnect Test and Repair. ITC Po-Yao Chuang, Cheng-Wen Wu, Erik Jan Marinissen
2025	A	`conf`	Chiplets' Die-to-Die Interconnect Repair Language (IRL). ITC Po-Yao Chuang, Erik Jan Marinissen
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	B	`conf`	Extendable E ETS Po-Yao Chuang, Erik Jan Marinissen
2025	J	`jnl`	Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Po-Yao Chuang, Francesco Lorenzelli, Cheng-Wen Wu, Erik Jan Marinissen
2025	J	`jnl`	Guest Editorial 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test - Part I. IEEE J. Emerg. Sel. Topics Circuits Syst. Qinfen Hao, Kuan-Neng Chen, Sandeep Kumar Goel, Hai Li, Erik Jan Marinissen
2025	J	`jnl`	Guest Editorial: 2.5-D/3-D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test - Part II. IEEE J. Emerg. Sel. Topics Circuits Syst. Qinfen Hao, Kuan-Neng Chen, Sandeep Kumar Goel, Hai Li, Erik Jan Marinissen
2024	J	`jnl`	Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology. IEEE Des. Test Zhan Gao, Min-Chun Hu, Rogier Baert, Bilal Chehab, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen
2024	B	`conf`	Design-for-Test for Intermittent Faults in STT-MRAMs. ETS Sicong Yuan, Mohammad Amin Yaldagard, Hanzhi Xun, Moritz Fieback, Erik Jan Marinissen, Woojin Kim, Siddharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui
2024	Misc	`conf`	IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair. VTS Erik Jan Marinissen, Vineet Pancholi, Po-Yao Chuang, Martin Keim
2024	B	`conf`	New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405. ETS Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra
2024	—	`conf`	Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers. IRPS Dishant Sangani, Ben Kaczer, Pieter Weckx, Philippe J. Roussel, Subrat Mishra, Erik Jan Marinissen, Georges G. E. Gielen
2024	B	`conf`	Silent Data Corruption: Test or Reliability Problem? ETS Erik Jan Marinissen, Harish Dattatraya Dixit, Ronald Shawn Blanton, Aaron Kuo, Wei Li, Subhasish Mitra, Chris Nigh, Ruben Purdy, Ben Kaczer, Dishant Sangani, Pieter Weckx, Philippe J. Roussel, Georges G. E. Gielen
2024	B	`conf`	Test and Repair Improvements for UCIe. ETS Tsung-Hsuan Wang, Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen
2024	A	`conf`	Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment? ITC Sicong Yuan, Hanzhi Xun, Woojin Kim, Siddharth Rao, Erik Jan Marinissen, Sebastien Couet, Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui
2023	—	`conf`	Device Aware Diagnosis for Unique Defects in STT-MRAMs. ATS Ahmed Aouichi, Sicong Yuan, Moritz Fieback, Siddharth Rao, Woojin Kim, Erik Jan Marinissen, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui
2023	A	`conf`	Device-Aware Test for Back-Hopping Defects in STT-MRAMs. DATE Sicong Yuan, Mottaqiallah Taouil, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, Said Hamdioui
2023	—	`conf`	Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen
2023	Misc	`conf`	Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen
2023	—	`conf`	Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency. ITC-Asia Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen
2023	Misc	`conf`	IP Session on Chiplet: Design, Assembly, and Test. VTS Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty
2023	A	`conf`	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs. ITC Sicong Yuan, Ziwei Zhang, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui
2023	—	`conf`	Moore Meets Murphy : Invited Talk 1. ITC-Asia Erik Jan Marinissen
2023	B	`conf`	Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. ETS Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen
2023	A	`conf`	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. ITC Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen
2022	J	`jnl`	A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability. IEEE Trans. Circuits Syst. II Express Briefs Xugang Cao, Hailong Jiao, Erik Jan Marinissen
2022	J	`jnl`	Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs. IEEE Trans. Computers Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
2022	J	`jnl`	Guest Editors' Introduction: Special Issue on Design and Test of Multidie Packages. IEEE Des. Test Adam Cron, Hailong Jiao, Erik Jan Marinissen
2022	J	`jnl`	MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
2022	J	`jnl`	Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. IEEE Des. Test Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Takuji Miki, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen
2021	J	`jnl`	Automated Probe-Mark Analysis for Advanced Probe Technology Characterization. IEEE Des. Test Yu-Rong Jian, Ferenc Fodor, Cheng-Wen Wu, Erik Jan Marinissen
2021	A	`conf`	Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM. DATE Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
2021	J	`jnl`	Defect and Fault Modeling Framework for STT-MRAM Testing. IEEE Trans. Emerg. Top. Comput. Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Guilherme Cardoso Medeiros, Moritz Fieback, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
2021	J	`jnl`	IEEE Standard 1838 Is on the Move. Computer Adam Cron, Erik Jan Marinissen
2021	J	`jnl`	Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality. J. Electron. Test. Zhan Gao, Min-Chun Hu, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Erik Jan Marinissen
2021	B	`conf`	Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis. ETS Francesco Lorenzelli, Zhan Gao, Joe Swenton, Santosh Malagi, Erik Jan Marinissen
2021	B	`conf`	Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring. ETS Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen
2021	A	`conf`	Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions. ITC Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
2020	B	`conf`	Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios. ETS Michele Stucchi, Ferenc Fodor, Erik Jan Marinissen
2020	A	`conf`	Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs. ITC Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
2020	A	`conf`	Impact of Magnetic Coupling and Density on STT-MRAM Performance. DATE Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
2020	J	`jnl`	Impact of Magnetic Coupling and Density on STT-MRAM Performance. CoRR Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
2020	J	`jnl`	Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests. CoRR Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui
2020	B	`conf`	Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults. ETS Min-Chun Hu, Zhan Gao, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Cheng-Wen Wu, Erik Jan Marinissen
2019	A	`conf`	Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library. ITC Zhan Gao, Santosh Malagi, Min-Chun Hu, Joe Swenton, Rogier Baert, Jos Huisken, Bilal Chehab, Kees Goossens, Erik Jan Marinissen
2019	—	`conf`	Defect-Location Identification for Cell-Aware Test. LATS Zhan Gao, Santosh Malagi, Erik Jan Marinissen, Joe Swenton, Jos Huisken, Kees Goossens
2019	A	`conf`	Device-Aware Test: A New Test Approach Towards DPPB Level. ITC Moritz Fieback, Lizhou Wu, Guilherme Cardoso Medeiros, Hassen Aziza, Siddharth Rao, Erik Jan Marinissen, Mottaqiallah Taouil, Said Hamdioui
2019	—	`conf`	Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices. ITC-Asia Zhan Gao, Min-Chun Hu, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen
2019	B	`conf`	Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. ETS Lizhou Wu, Siddharth Rao, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen, Farrukh Yasin, Sebastien Couet, Said Hamdioui, Gouri Sankar Kar
2019	—	`conf`	Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 3DIC Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne
2018	—	`conf`	Automatic Generation of In-Circuit Tests for Board Assembly Defects. ITC-Asia Harm van Schaaijk, Martien Spierings, Erik Jan Marinissen
2018	B	`conf`	Automatic generation of in-circuit tests for board assembly defects. ETS Harm van Schaaijk, Martien Spierings, Erik Jan Marinissen
2018	A	`conf`	Electrical Modeling of STT-MRAM Defects. ITC Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui
2018	B	`conf`	IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers. ETS Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, Erik Jan Marinissen
2018	A	`conf`	On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs. ITC Leonidas Katselas, Alkis A. Hatzopoulos, Hailong Jiao, Christos Papameletis, Erik Jan Marinissen
2018	A	`conf`	Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. ITC Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu
2017	—	`conf`	A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards. ITC-Asia Erik Jan Marinissen, Ferenc Fodor, Bart De Wachter, Jorg Kiesewetter, Eric Hill, Ken Smith
2017	—	`conf`	Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs. PATMOS Leonidas Katselas, Hailong Jiao, Angelos Athanasiadis, Christos Papameletis, Alkis A. Hatzopoulos, Erik Jan Marinissen
2017	J	`jnl`	Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory. IEEE Des. Test Erik Jan Marinissen, Yervant Zorian
2016	J	`jnl`	Guest Editors' Introduction: Robust 3-D Stacked ICs. IEEE Des. Test S. Saqib Khursheed, Pascal Vivet, Fabian Hopsch, Erik Jan Marinissen
2016	B	`conf`	IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs. ETS Erik Jan Marinissen, Teresa L. McLaurin, Hailong Jiao
2016	B	`conf`	IoT: Source of test challenges. ETS Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes
2016	B	`conf`	Test-station for flexible semi-automatic wafer-level silicon photonics testing. ETS Jeroen De Coster, Peter De Heyn, Marianna Pantouvaki, Brad Snyder, Hongtao Chen, Erik Jan Marinissen, Philippe Absil, Joris Van Campenhout, Bryan Bolt
2015	J	`jnl`	A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. IEEE Des. Test Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen
2015	J	`jnl`	Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption. IEEE Trans. Computers Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen
2015	—	`conf`	Active-lite interposer for 2.5 & 3D integration. VLSIC Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean
2015	—	`conf`	At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. ATS Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen
2015	A	`conf`	Automated testing of bare die-to-die stacks. ITC Erik Jan Marinissen, Bart De Wachter, Teng Wang, Jens Fiedler, Jorg Kiesewetter, Karsten Stoll
2015	J	`jnl`	Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen
2015	—	`conf`	Processing active devices on Si interposer and impact on cost. 3DIC Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne
2015	J	`jnl`	Robust Optimization of Test-Access Architectures Under Realistic Scenarios. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen
2015	J	`jnl`	Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching. ACM Trans. Design Autom. Electr. Syst. Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
2014	A	`conf`	Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface. ITC Erik Jan Marinissen, Bart De Wachter, Ken Smith, Jorg Kiesewetter, Mottaqiallah Taouil, Said Hamdioui
2014	A	`conf`	Interconnect test for 3D stacked memory-on-logic. DATE Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen
2014	J	`jnl`	Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2014	Misc	`conf`	Quality versus cost analysis for 3D Stacked ICs. VTS Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
2014	A	`conf`	Vesuvius-3D: A 3D-DfT demonstrator. ITC Erik Jan Marinissen, Bart De Wachter, Stephen O'Loughlin, Sergej Deutsch, Christos Papameletis, Tobias Burgherr
2013	B	`conf`	Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. ETS Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui
2013	C	`conf`	Creating options for 3D-SIC testing. DDECS Erik Jan Marinissen
2013	—	`conf`	Creating options for 3D-SIC testing. VLSI-DAT Erik Jan Marinissen
2013	—	`conf`	Design issues in heterogeneous 3D/2.5D integration. ASP-DAC Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne
2013	—	`conf`	Impact of mid-bond testing in 3D stacked ICs. DFTS Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik
2013	—	`conf`	Murphy goes 3D. ISVLSI Erik Jan Marinissen
2013	—	`conf`	Si interposer build-up options and impact on 3D system cost. 3DIC Dimitrios Velenis, Mikael Detalle, Erik Jan Marinissen, Eric Beyne
2013	A	`conf`	Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs. ITC Sergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen
2013	—	`conf`	Using 3D-COSTAR for 2.5D test cost optimization. 3DIC Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik
2012	J	`jnl`	A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper. J. Electron. Test. Erik Jan Marinissen, Chun-Chuan Chi, Mario Konijnenburg, Jouke Verbree
2012	A	`conf`	Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs. DATE Erik Jan Marinissen
2012	A	`conf`	DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen
2012	A	`conf`	EDA solutions to new-defect detection in advanced process technologies. DATE Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl
2012	J	`jnl`	Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits. J. Electron. Test. Erik Jan Marinissen, Yervant Zorian
2012	J	`jnl`	Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J. Electron. Test. Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen
2012	J	`jnl`	Pioneering in Asia With the US Venture Capital Model. IEEE Des. Test Comput. Erik Jan Marinissen
2012	J	`jnl`	Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost. J. Electron. Test. Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen
2011	—	`conf`	Automation of 3D-DfT Insertion. Asian Test Symposium Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel
2011	B	`conf`	DfT Architecture for 3D-SICs with Multiple Towers. ETS Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011	A	`conf`	Evaluation of TSV and micro-bump probing for wide I/O testing. ITC Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel
2011	—	`conf`	Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011	—	`conf`	On modeling and optimizing cost in 3D Stacked-ICs. IDT Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
2011	A	`conf`	Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011	J	`jnl`	Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree
2011	—	`ch.`	Testing 3D Stacked ICs Containing Through-Silicon Vias. 3D Integration for NoC-based SoC Architectures Erik Jan Marinissen
2010	—	`conf`	3D DfT architecture for pre-bond and post-bond testing. 3DIC Erik Jan Marinissen, Chun-Chuan Chi, Jouke Verbree, Mario Konijnenburg
2010	C	`conf`	3D integration: Circuit design, test, and reliability challenges. IOLTS Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal
2010	Misc	`conf`	A structured and scalable test access architecture for TSV-based 3D stacked ICs. VTS Erik Jan Marinissen, Jouke Verbree, Mario Konijnenburg
2010	A	`conf`	Adapting to adaptive testing. DATE Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli
2010	J	`jnl`	Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism. J. Electron. Test. Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens
2010	—	`conf`	Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access. APCCAS Erik Jan Marinissen
2010	—	`conf`	Cost effectiveness of 3D integration options. 3DIC Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne
2010	A	`conf`	On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs. ITC Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen
2010	B	`conf`	On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. ETS Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis
2010	A	`conf`	Optimization methods for post-bond die-internal/external testing in 3D stacked ICs. ITC Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen
2010	—	`conf`	Test Cost Analysis for 3D Die-to-Wafer Stacking. Asian Test Symposium Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen
2010	B	`conf`	Test-architecture optimization for TSV-based 3D stacked ICs. ETS Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree
2010	A	`conf`	Testing TSV-based three-dimensional stacked ICs. DATE Erik Jan Marinissen
2009	A	`conf`	Contactless testing: Possibility or pipe-dream? DATE Erik Jan Marinissen, Dae Young Lee, John P. Hayes, Chris Sellathamby, Brian Moore, Steven Slupsky, Laurence Pujol
2009	J	`jnl`	Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2. IEEE Des. Test Comput. Erik Jan Marinissen, Yervant Zorian
2009	J	`jnl`	Guest Editors' Introduction: The Status of IEEE Std 1500. IEEE Des. Test Comput. Erik Jan Marinissen, Yervant Zorian
2009	J	`jnl`	IEEE Std 1500 Enables Modular SoC Testing. IEEE Des. Test Comput. Erik Jan Marinissen, Yervant Zorian
2009	—	`conf`	Impact of 3D design choices on manufacturing cost. 3DIC Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne
2009	—	`conf`	On Scan Chain Diagnosis for Intermittent Faults. Asian Test Symposium Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, Erik Larsson
2009	J	`jnl`	Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Des. Test Comput. Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
2009	A	`conf`	Testing 3D chips containing through-silicon vias. ITC Erik Jan Marinissen, Yervant Zorian
2009	J	`jnl`	Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Trans. Computers Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty
2008	A	`conf`	Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. DATE Ozgur Sinanoglu, Erik Jan Marinissen
2008	B	`conf`	Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism. ETS Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens
2008	J	`jnl`	Bugs, moths, grasshoppers, and whales. IEEE Des. Test Comput. Erik Jan Marinissen
2008	J	`jnl`	Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis. IEEE Des. Test Comput. Rob Aitken, Erik Jan Marinissen
2007	J	`jnl`	DATE 07 workshop on diagnostic services in NoCs. IEEE Des. Test Comput. Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici
2007	A	`conf`	Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. DATE Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters
2007	J	`jnl`	Editorial Silicon Debug and Diagnosis. IET Comput. Digit. Tech. Erik Jan Marinissen, Nicola Nicolici
2007	J	`jnl`	Editorial. IET Comput. Digit. Tech. Christian Landrault, Erik Jan Marinissen
2007	A	`conf`	Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects. ITC Jeroen Geuzebroek, Erik Jan Marinissen, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke
2007	J	`jnl`	On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips CoRR Sandeep Kumar Goel, Erik Jan Marinissen
2007	A	`conf`	Test quality analysis and improvement for an embedded asynchronous FIFO. DATE Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters
2007	J	`jnl`	Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. IET Comput. Digit. Tech. Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes
2006	J	`jnl`	Conference Reports. IEEE Des. Test Comput. Subhasish Mitra, Ondrej Novák, Hana Kubátová, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar
2006	A	`conf`	Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2006	B	`conf`	Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. ETS Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes
2005	A	`conf`	Challenges in Embedded Memory Design and Test. DATE Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian
2005	—	`conf`	IEEE Std 1500 Compliant Infrastructure forModular SOC Testing. Asian Test Symposium Tom Waayers, Erik Jan Marinissen, Maurice Lousberg
2005	A	`conf`	On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. DATE Sandeep Kumar Goel, Erik Jan Marinissen
2005	J	`jnl`	Optimal Interconnect ATPG Under a Ground-Bounce Constraint. J. Electron. Test. Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
2005	B	`conf`	Test scheduling for modular SOCs in an abort-on-fail environment. ETS Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen
2004	A	`conf`	IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ITC Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2004	—	`conf`	Infrastructure for modular SOC testing. CICC Erik Jan Marinissen, Tom Waayers
2004	A	`conf`	Security vs. Test Quality: Can We Really Only Have One at a Time? ITC Erik Jan Marinissen
2004	A	`conf`	Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. DATE Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk
2004	A	`conf`	Trends in Testing Integrated Circuits. ITC Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge
2004	B	`conf`	User-constrained test architecture design for modular SOC testing. ETS Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre
2003	J	`jnl`	A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. J. Electron. Test. Sandeep Kumar Goel, Erik Jan Marinissen
2003	—	`conf`	Control-aware test architecture design for modular SOC testing. ETW Sandeep Kumar Goel, Erik Jan Marinissen
2003	A	`conf`	Creating Value Through Test. DATE Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller
2003	J	`jnl`	Efficient test access mechanism optimization for system-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2003	A	`conf`	Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. DATE Sandeep Kumar Goel, Erik Jan Marinissen
2003	J	`jnl`	Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. IEEE Des. Test Comput. Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts
2003	A	`conf`	Optimal Interconnect ATPG Under a Ground-Bounce Constraint. ITC Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
2003	J	`jnl`	SOC test architecture design for efficient utilization of test bandwidth. ACM Trans. Design Autom. Electr. Syst. Sandeep Kumar Goel, Erik Jan Marinissen
2003	J	`jnl`	Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. IEEE Trans. Computers Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2003	—	`conf`	Yield analysis for repairable embedded memories. ETW Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty
2002	A	`conf`	A Set of Benchmarks fo Modular Testing of SOCs. ITC Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty
2002	—	`conf`	A novel test time reduction algorithm for test architecture design for core-based system chips. ETW Sandeep Kumar Goel, Erik Jan Marinissen
2002	Misc	`conf`	Cluster-Based Test Architecture Design for System-on-Chip. VTS Sandeep Kumar Goel, Erik Jan Marinissen
2002	A	`conf`	Effective and Efficient Test Architecture Design for SOCs. ITC Sandeep Kumar Goel, Erik Jan Marinissen
2002	A	`conf`	Efficient Wrapper/TAM Co-Optimization for Large SOCs. DATE Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2002	J	`jnl`	How Useful are the ITC 02 SoC Test Benchmarks? IEEE Des. Test Comput. Krishnendu Chakrabarty, Erik Jan Marinissen
2002	J	`jnl`	On IEEE P1500's Standard for Embedded Core Test. J. Electron. Test. Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian
2002	Misc	`conf`	On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. VTS Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2002	—	`conf`	Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. Asian Test Symposium Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2002	A	`conf`	Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2002	J	`jnl`	Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. J. Electron. Test. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2002	J	`jnl`	The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs. J. Electron. Test. Erik Jan Marinissen
2002	A*	`conf`	Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. DAC Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2001	C	`conf`	An Industrial Approach to Core-Based System Chip Testing. VLSI-SOC Erik Jan Marinissen
2001	J	`jnl`	Application of Deterministic Logic BIST on Industrial Circuits. J. Electron. Test. Gundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich
2001	A	`conf`	Test wrapper and test access mechanism co-optimization for system-on-chip. ITC Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2001	—	`conf`	Testing Embedded Core-Based System Chips. LATW Erik Jan Marinissen, Yervant Zorian
2000	A	`conf`	Application of deterministic logic BIST on industrial circuits. ITC Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen
2000	A	`conf`	On using IEEE P1500 SECT for test plug-n-play. ITC Yervant Zorian, Erik Jan Marinissen, Rohit Kapur
2000	A*	`conf`	System chip test: how will it impact your design? DAC Yervant Zorian, Erik Jan Marinissen
2000	A	`conf`	Wrapper design for embedded core test. ITC Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel
1999	J	`jnl`	Challenges in testing core-based system ICs. IEEE Commun. Mag. Erik Jan Marinissen, Yervant Zorian
1999	J	`jnl`	Testing Embedded-Core-Based System Chips. Computer Yervant Zorian, Erik Jan Marinissen, Sujit Dey
1999	—	`conf`	The role of test protocols in testing embedded-core-based system ICs. ETW Erik Jan Marinissen, Maurice Lousberg
1999	A	`conf`	Towards a standard for embedded core test: an example. ITC Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel
1998	A	`conf`	A structured and scalable mechanism for test access to embedded reusable cores. ITC Erik Jan Marinissen, Robert G. J. Arendsen, Gerard Bos, Hans Dingemanse, Maurice Lousberg, Clemens Wouters
1998	A	`conf`	Scan chain design for test time reduction in core-based ICs. ITC Joep Aerts, Erik Jan Marinissen
1998	A	`conf`	Testing embedded-core based system chips. ITC Yervant Zorian, Erik Jan Marinissen, Sujit Dey