Erich Barke - RankMe

85 papers A* 8A 20B 7C 15Misc 1Journal 5Unranked 28

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Hierarchical Verification of AMS Systems With Affine Arithmetic Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Carna Zivkovic, Christoph Grimm, Markus Olbrich, Oliver Scharf, Erich Barke
2018	C	`conf`	STP - A Quadratic VLSI Placement Tool Using Graphic Processing Units. ISPDC Bjorn Bredthauer, Markus Olbrich, Erich Barke
2016	A	`conf`	Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. DATE Erich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher
2015	—	`conf`	Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits. ASP-DAC Hyun-Sek Lukas Lee, Matthias Althoff, Stefan Hoelldampf, Markus Olbrich, Erich Barke
2015	C	`conf`	Fast global interconnnect driven 3D floorplanning. VLSI-SoC Artur Quiring, Markus Olbrich, Erich Barke
2015	—	`conf`	Split and merge strategies for solving uncertain equations using affine arithmetic. SimuTools Oliver Scharf, Markus Olbrich, Erich Barke
2014	A	`conf`	Application of Mission Profiles to enable cross-domain constraint-driven design. DATE C. Katzschke, M.-P. Sohn, Markus Olbrich, Volker Meyer zu Bexten, Markus Tristl, Erich Barke
2014	—	`conf`	Simulation Based Verification with Range Based Signal Representations for Mixed-Signal Systems. SBCCI Michael Kärgel, Markus Olbrich, Erich Barke
2013	—	`conf`	Improving 3D-Floorplanning using smart selection operations in meta-heuristic optimization. 3DIC Artur Quiring, Markus Olbrich, Erich Barke
2012	—	`conf`	Efficient generation of analog circuit models for accelerated mixed-signal simulation. SoCC Stefan Hoelldampf, Hyun-Sek Lukas Lee, Daniel Zaum, Markus Olbrich, Erich Barke
2011	—	`conf`	3D floorplanning considering vertically aligned rectilinear modules using T 3DIC Artur Quiring, Marc Lindenberg, Markus Olbrich, Erich Barke
2011	Misc	`conf`	A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization. VLSI Design Min Zhang, R. Häußler, Markus Olbrich, Harald Kinzelbach, Erich Barke
2011	—	`conf`	A gate sizing method for glitch power reduction. SoCC Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz
2011	A	`conf`	A theoretical probabilistic simulation framework for dynamic power estimation. ICCAD Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz
2011	C	`conf`	Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation. ICCD Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke
2010	C	`conf`	An Accelerated Mixed-Signal Simulation Kernel for SystemC. FDL Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann
2010	C	`conf`	Towards Abstract Analysis Techniques for Range Based System Simulations. FDL Florian Schupfer, Christoph Grimm, Markus Olbrich, Michael Kärgel, Erich Barke
2009	—	`conf`	Fast dynamic power estimation considering glitch filtering. SoCC Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler
2009	A	`conf`	Formal approaches to analog circuit verification. DATE Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang
2009	—	`conf`	The PRAISE approach for accelerated transient analysis applied to wire models. BMAS Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt
2008	C	`conf`	A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. DDECS Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke
2008	—	`conf`	Analog circuit simulation using range arithmetics. ASP-DAC Darius Grabowski, Markus Olbrich, Erich Barke
2008	—	`conf`	Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl
2008	A	`conf`	Determining the Technical Complexity of Integrated Circuits. DATE Peter Leppelt, Erich Barke
2008	—	`conf`	Distribution arithmetic for stochastical analysis. ASP-DAC Markus Olbrich, Erich Barke
2008	C	`conf`	Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). FDL Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt
2007	—	`conf`	Algorithms for automatic length compensation of busses in analog integrated circuits. ISPD Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten
2007	A	`conf`	CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. DATE Min Zhang, Markus Olbrich, David Seider, Martin Frerichs, Harald Kinzelbach, Erich Barke
2007	A*	`conf`	Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. DAC Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke
2007	B	`conf`	Incremental Fault Emulation. FPL Jan Torben Weinkopf, Klaus Harbich, Erich Barke
2007	C	`conf`	Range Arithmetics to Speed up Reachability Analysis of Analog Systems. FDL Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke
2007	—	`conf`	Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl
2006	—	`conf`	Ansätze zur Verbesserung der Simulationsperformance automatisch generierter analoger Verhaltensmodelle. MBMV Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke
2006	—	`conf`	Ein Verfahren zur effizienten Analyse von Schaltungen mit Parametervarianzen. MBMV Darius Grabowski, Christoph Grimm, Erich Barke
2006	B	`conf`	Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. FPL Jan Torben Weinkopf, Klaus Harbich, Erich Barke
2006	C	`conf`	Semi-symbolic modeling and simulation of circuits and systems. ISCAS Darius Grabowski, Christoph Grimm, Erich Barke
2006	C	`conf`	Using Sequential Equations to Improve Efficiency and Robustness. FDL Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke
2006	—	`conf`	Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen. MBMV Ralf Klausen, Lars Hedrich, Erich Barke
2005	—	`conf`	Routing of analog busses with parasitic symmetry. ISPD Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten
2005	—	`conf`	Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. FAC Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke
2004	A	`conf`	Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. DATE Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke
2004	A	`conf`	Placement Using a Localization Probability Model (LPM). DATE Markus Olbrich, Erich Barke
2004	—	`conf`	Wirelength Reduction Using 3-D Physical Design. PATMOS Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke
2003	—	`conf`	Placing substrate contacts into mixed-signal circuits controlling circuit performance. CICC Andreas Hermann, Markus Olbrich, Erich Barke
2003	C	`conf`	Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. VLSI-SOC Andreas Hermann, Markus Olbrich, Erich Barke
2002	A	`conf`	A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . DATE Joerg Abke, Erich Barke
2002	A	`conf`	An Approach to Model Checking for Nonlinear Analog Systems. DATE Walter Hartong, Lars Hedrich, Erich Barke
2002	—	`conf`	An Upper Bound for 3D Slicing Floorplans. ASP-DAC/VLSI Design Silke Salewski, Erich Barke
2002	A	`conf`	Analog circuit sizing based on formal methods using affine arithmetic. ICCAD Andreas C. Lemke, Lars Hedrich, Erich Barke
2002	A*	`conf`	Model checking algorithms for analog verification. DAC Walter Hartong, Lars Hedrich, Erich Barke
2002	A*	`conf`	On Discrete Modeling and Model Checking for Nonlinear Analog Systems. CAV Walter Hartong, Lars Hedrich, Erich Barke
2002	A	`conf`	Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. DATE Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke
2001	B	`conf`	A New Placement Method for Direct Mapping into LUT-Based FPGAs. FPL Joerg Abke, Erich Barke
2001	A	`conf`	An improved hierarchical classification algorithm for structural analysis of integrated circuits. DATE Markus Olbrich, Achim Rein, Erich Barke
2001	A	`conf`	Architecture driven partitioning. DATE Joachim Küter, Erich Barke
2001	—	`conf`	CHIPDESIGN - A Novel Project-oriented Microelectronics Course. MSE Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch
2001	B	`conf`	PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. FPL Klaus Harbich, Erich Barke
2000	A*	`conf`	A current driven routing and verification methodology for analog applications. DAC Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke
2000	B	`conf`	CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. FPL Joerg Abke, Erich Barke
2000	—	`ed.`	Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings PATMOS Dimitrios Soudris, Peter Pirsch, Erich Barke
2000	—	`conf`	PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. PATMOS Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel
2000	A	`conf`	Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. DATE Thorsten Adler, Erich Barke
2000	A	`conf`	Static Timing Analysis Taking Crosstalk into Account. DATE Matthias Ringe, Thomas Lindenkreuz, Erich Barke
1999	C	`conf`	A Case Study: Logic Emulation - Pitfalls and Solutions. IEEE International Workshop on Rapid System Prototyping Klaus Harbich, Jörn Stohmann, Erich Barke, Ludwig Schwoerer
1999	C	`conf`	A Universal Module Generator for LUT-Based FPGAs. IEEE International Workshop on Rapid System Prototyping Joerg Abke, Erich Barke, Jörn Stohmann
1999	—	`conf`	An extended bipolar transistor model for substrate crosstalk analysis. CICC M. Klemme, Erich Barke
1998	A	`conf`	A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. DATE Lars Hedrich, Erich Barke
1998	B	`conf`	An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. FPL Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke
1998	A	`conf`	Path Verification Using Boolean Satisfiability. DATE Matthias Ringe, Thomas Lindenkreuz, Erich Barke
1998	—	`conf`	Real Time Fault Injection Using Logic Emulators. ASP-DAC Reza Sedaghat-Maman, Erich Barke
1997	C	`conf`	A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. ICCD Jörn Stohmann, Erich Barke
1997	C	`conf`	A new approach to fault emulation. IEEE International Workshop on Rapid System Prototyping Reza Sedaghat-Maman, Erich Barke
1997	—	`conf`	Design driven partitioning. ASP-DAC Dirk Behrens, Erich Barke, Robert Tolkiehn
1996	B	`conf`	A Universal CLA Adder Generator for SRAM-Based FPGAs. FPL Jörn Stohmann, Erich Barke
1996	A*	`conf`	Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. DAC Carsten Borchers, Lars Hedrich, Erich Barke
1996	A	`conf`	Hierarchical partitioning. ICCAD Dirk Behrens, Klaus Harbich, Erich Barke
1996	—	`conf`	PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor. ED&TC Frank Scherber, Erich Barke, Wolfgang Meier
1995	A	`conf`	A formal approach to nonlinear analog circuit verification. ICCAD Lars Hedrich, Erich Barke
1988	J	`jnl`	Line-to-ground capacitance calculation for VLSI: a comparison. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Erich Barke
1985	J	`jnl`	FERKEL: Technologieunabhängiges direktivengesteuertes Programmsystem zur Entwurfsregelnprüfung. Angew. Inform. Erich Barke
1985	A*	`conf`	Resistance calculation from mask artwork data by finite element method. DAC Erich Barke
1984	J	`jnl`	A Network Comparison Algorithm for Layout Verification of Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Erich Barke
1984	A*	`conf`	A technology independent block extraction algorithm. DAC F. Luellau, T. Hoepken, Erich Barke
1984	J	`jnl`	Figurenorientierte boolesche Maskenoperationen für die Layout-Prüfung integrierter Schaltungen / Polygon-based boolean mask operations to be used in IC design rule checking. Elektron. Rechenanlagen Erich Barke
1983	A*	`conf`	A layout verification system for analog bipolar integrated circuits. DAC Erich Barke