Erica Tena-Sánchez

27 papers C 4Journal 12Unranked 11
YearRankTypeTitle / Venue / Authors
2025 — conf
Low Entropy Masking Protection Scheme for Ascon Cipher to Counteract Side-Channel Attacks.
DCIS
Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Miguel Martín-González, Alejandro Casado-Galán, Antonio J. Acosta
2025 — conf
TERORO - Transient Effect Ring Oscillator and Ring Oscillator Configurable Hybrid PUF.
SMACD
Alejandro Casado-Galán, J. Núñez-Martínez, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Antonio J. Acosta
2024 — conf
Cryptographic Security Through a Hardware Root of Trust.
ARC
Luis F. Rojas-Muñoz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Eros Camacho-Ruiz, Pablo Navarro-Torrero, Apurba Karmakar, Carlos Fernández García, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Alejandro Casado-Galán, Pau Ortega-Castro, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández, Piedad Brox
2024 C conf
Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher.
DSD
Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Virginia Zúñiga-González, Antonio J. Acosta
2024 — conf
Electromagnetic Fault Injection Attack Methodology against AES Hardware Implementation.
DCIS
Alejandro Casado-Galán, Francisco Eugenio Potestad-Ordóñez, Antonio J. Acosta, Erica Tena-Sánchez
2024 — conf
Hardware implementations, SCA/FIA attacks, and countermeasures for the ASCON AEAD cipher: a review.
DCIS
Miguel Martín-González, Erica Tena-Sánchez, F. Eugenio Potestad Ordóñez, Antonio J. Acosta
2024 J jnl
Protecting FPGA-Based Cryptohardware Implementations from Fault Attacks Using ADCs.
Sensors
Francisco Eugenio Potestad-Ordóñez, Alejandro Casado-Galán, Erica Tena-Sánchez
2023 — conf
A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks.
DCIS
Virginia Zúñiga-González, Erica Tena-Sánchez, Antonio J. Acosta
2023 — conf
A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem.
DCIS
Eros Camacho-Ruiz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Erica Tena-Sánchez, Piedad Brox
2022 J jnl
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher.
IEEE Access
Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Antonio J. Acosta, Carlos Jesús Jiménez-Fernández, Ricardo Chaves
2022 J jnl
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs.
IEEE Embed. Syst. Lett.
Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
2021 J jnl
Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices.
IEEE Trans. Emerg. Top. Comput.
Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
2021 J jnl
Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.
Sensors
Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández
2021 J jnl
Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA.
IEEE Access
Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández
2020 C conf
Hamming-Code Based Fault Detection Design Methodology for Block Ciphers.
ISCAS
Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Ricardo Chaves, Manuel Valencia-Barrero, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández
2020 J jnl
Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies.
ACM J. Emerg. Technol. Comput. Syst.
Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
2019 J jnl
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks.
Int. J. Circuit Theory Appl.
Erica Tena-Sánchez, Antonio J. Acosta
2018 — conf
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits.
DCIS
Erica Tena-Sánchez, Ignacio M. Delgado-Lozano, Juan Núñez, Antonio J. Acosta
2018 — conf
Effect of Temperature Variation in Experimental DPA and DEMA Attacks.
PATMOS
Erica Tena-Sánchez, Antonio J. Acosta
2017 J jnl
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview.
Int. J. Circuit Theory Appl.
Antonio J. Acosta, Tommaso Addabbo, Erica Tena-Sánchez
2017 J jnl
Power and Energy Issues on Lightweight Cryptography.
J. Low Power Electron.
Antonio J. Acosta, Erica Tena-Sánchez, Carlos Jesús Jiménez-Fernández, Javier M. Mora-Merchan
2016 J jnl
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions.
Int. J. Circuit Theory Appl.
Piedad Brox, Macarena C. Martínez-Rodríguez, Erica Tena-Sánchez, Iluminada Baturone, Antonio J. Acosta
2016 — conf
Secure cryptographic hardware implementation issues for high-performance applications.
PATMOS
Erica Tena-Sánchez, Antonio J. Acosta, Juan Núñez
2015 C conf
DPA vulnerability analysis on Trivium stream cipher using an optimized power model.
ISCAS
Erica Tena-Sánchez, Antonio J. Acosta
2014 J jnl
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta
2014 — conf
Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications.
PATMOS
Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta
2014 C conf
Low-Power Differential Logic Gates for DPA Resistant Circuits.
DSD
Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta