Eric Rotenberg

69 papers A* 24A 4B 6C 6Misc 3Journal 11Unranked 15
YearRankTypeTitle / Venue / Authors
2025 A* conf
CryptoBTB: A Secure Hierarchical BTB for Diverse Instruction Footprint Workloads.
MICRO
Debpratim Adak, Eric Rotenberg, Amro Awad, Huiyang Zhou
2025 A* conf
Delinquent Loop Pre-execution Using Predicated Helper Threads.
HPCA
Anirudh Seshadri, Eric Rotenberg
2025 A* conf
SpecMPK: Efficient In-Process Isolation with Speculative and Secure Permission Update Instruction.
HPCA
Debpratim Adak, Huiyang Zhou, Eric Rotenberg, Amro Awad
2021 A* conf
Post-Fabrication Microarchitecture.
MICRO
Chanchal Kumar, Anirudh Seshadri, Aayush Chaudhary, Shubham Bhawalkar, Rohit Singh, Eric Rotenberg
2020 J jnl
Post-Silicon Microarchitecture.
IEEE Comput. Archit. Lett.
Chanchal Kumar, Aayush Chaudhary, Shubham Bhawalkar, Utkarsh Mathur, Saransh Jain, Adith Vastrad, Eric Rotenberg
2020 A* conf
Slipstream Processors Revisited: Exploiting Branch Sets.
ISCA
Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Eric Rotenberg
2017 — conf
A case for standard-cell based RAMs in highly-ported superscalar processor structures.
ISQED
Sungkwan Ku, Elliott Forbes, Rangeen Basu Roy Chowdhury, Eric Rotenberg
2017 C conf
H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor.
ICCD
Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon
2016 — conf
AnyCore-1: A comprehensively adaptive 4-way superscalar processor.
Hot Chips Symposium
Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Eric Rotenberg
2016 B conf
AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores.
ISPASS
Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Sungkwan Ku, Eric Rotenberg
2016 C conf
Fast register consolidation and migration for heterogeneous multi-core processors.
ICCD
Elliott Forbes, Eric Rotenberg
2016 — conf
Physical design of a 3D-stacked heterogeneous multi-core processor.
3DIC
Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon
2015 — conf
Computing in 3D.
3DIC
Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Marcus Tshibangu, Steve Lipa
2015 — conf
Computing in 3D.
CICC
Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Steve Lipa
2015 J jnl
Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching.
IEEE Trans. Computers
Rami Sheikh, James Tuck, Eric Rotenberg
2015 — conf
Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor.
Hot Chips Symposium
Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon H. Dwiel, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon
2014 — conf
3D-enabled customizable embedded computer (3DECC).
3DIC
Paul D. Franzon, Eric Rotenberg, James Tuck, Huiyang Zhou, W. Rhett Davis, Hongwen Dai, Joonmoo Huh, Sungkwan Ku, Steve Lipa, Chao Li, Jong Beom Park, Joshua Schabel
2014 — conf
Co-simulation framework for streamlining microprocessor development on standard ASIC design flow.
ASP-DAC
Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo
2014 C conf
Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores.
ICCD
Elliott Forbes, Niket Kumar Choudhary, Brandon H. Dwiel, Eric Rotenberg
2013 B conf
A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors.
PACT
Sandeep Navada, Niket K. Choudhary, Salil V. Wadhavkar, Eric Rotenberg
2013 — conf
Design of controller for L2 cache mapped in Tezzaron stacked DRAM.
3DIC
Nyunyi M. Tshibangu, Paul D. Franzon, Eric Rotenberg, William Rhett Davis
2013 — conf
Hetero
ISQED
Shivam Priyadarshi, Niket K. Choudhary, Brandon H. Dwiel, Ankita Upreti, Eric Rotenberg, William Rhett Davis, Paul D. Franzon
2013 C conf
Rationale for a 3D heterogeneous multi-core processor.
ICCD
Eric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi M. Tshibangu, Steve Lipa, W. Rhett Davis, Paul D. Franzon
2012 C conf
A physical design study of fabscalar-generated superscalar cores.
VLSI-SoC
Niket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg
2012 A* conf
Control-Flow Decoupling.
MICRO
Rami Sheikh, James Tuck, Eric Rotenberg
2012 B conf
FPGA modeling of diverse superscalar processors.
ISPASS
Brandon H. Dwiel, Niket Kumar Choudhary, Eric Rotenberg
2012 J jnl
FabScalar: Automating Superscalar Core Design.
IEEE Micro
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg
2011 A* conf
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template.
ISCA
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg
2010 B conf
Criticality-driven superscalar design space exploration.
PACT
Sandeep Navada, Niket Kumar Choudhary, Eric Rotenberg
2010 — conf
EXACT: explicit dynamic-branch prediction with active updates.
Conf. Computing Frontiers
Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg
2009 A* conf
Architectural Contesting.
HPCA
Hashem Hashemi Najaf-abadi, Eric Rotenberg
2009 B conf
Core-Selectability in Chip Multiprocessors.
PACT
Hashem Hashemi Najaf-abadi, Niket Kumar Choudhary, Eric Rotenberg
2009 — conf
The importance of accurate task arrival characterization in the design of processing cores.
IISWC
Hashem Hashemi Najaf-abadi, Eric Rotenberg
2008 B conf
Configurational Workload Characterization.
ISPASS
Hashem Hashemi Najaf-abadi, Eric Rotenberg
2008 A conf
Coverage of a microarchitecture-level fault check regimen in a superscalar processor.
DSN
Vimal K. Reddy, Eric Rotenberg
2007 J jnl
Architectural
SIGARCH Comput. Archit. News
Hashem Hashemi Najaf-abadi, Eric Rotenberg
2007 A conf
Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance.
DSN
Vimal K. Reddy, Eric Rotenberg
2007 A* conf
Transparent control independence (TCI).
ISCA
Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary
2007 J jnl
ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling.
IEEE Trans. Computers
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg
2006 C conf
Assertion-Based Microarchitecture Design for Improved Reliability.
ICCD
Vimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi
2006 J jnl
FAST: Frequency-aware static timing analysis.
ACM Trans. Embed. Comput. Syst.
Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg
2006 J jnl
Non-uniform program analysis & repeatable execution constraints: exploiting out-of-order processors in real-time systems.
SIGBED Rev.
Aravindh Anantaraman, Eric Rotenberg
2006 A* conf
Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM.
HPCA
Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg
2006 — conf
The State of ZettaRAM.
Nano-Net
Eric Rotenberg, Ravi V. Venkatesan
2006 A* conf
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance.
ASPLOS
Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy
2005 A* conf
Tapping ZettaRAM
HPCA
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg
2005 Misc conf
Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing.
CASES
Ali El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg
2004 J jnl
A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors.
IEEE Trans. Computers
Jinson Koppanalil, Eric Rotenberg
2004 A conf
Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA).
RTSS
Aravindh Anantaraman, Kiran Seth, Eric Rotenberg, Frank Mueller
2004 Misc conf
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems.
CASES
Ali El-Haj-Mahmoud, Eric Rotenberg
2003 J jnl
Adaptive mode control: A static-power-efficient cache design.
ACM Trans. Embed. Comput. Syst.
Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
2003 A conf
FAST: Frequency-Aware Static Timing Analysis.
RTSS
Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg
2003 A* conf
Slipstream Execution Mode for CMP-Based Multiprocessors.
HPCA
Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg
2003 A* conf
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems.
ISCA
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller
2002 A* conf
A Large, Fast Instruction Window for Tolerating Cache Misses.
ISCA
Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan
2002 Misc conf
A case for dynamic pipeline scaling.
CASES
Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg
2001 — conf
Adaptive Mode Control: A Static-Power-Efficient Cache Design.
IEEE PACT
Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
2001 A* conf
Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems.
MICRO
Eric Rotenberg
2000 A* conf
A study of slipstream processors.
MICRO
Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg
2000 J jnl
Control Independence in Trace Processors.
J. Instr. Level Parallelism
Eric Rotenberg, James E. Smith
2000 A* conf
Slipstream Processors: Improving both Performance and Fault Tolerance.
ASPLOS
Karthik Sundaramoorthy, Zachary Purser, Eric Rotenberg
1999 A* conf
A Study of Control Independence in Superscalar Processors.
HPCA
Eric Rotenberg, Quinn Jacobson, James E. Smith
1999 J jnl
A Trace Cache Microarchitecture and Evaluation.
IEEE Trans. Computers
Eric Rotenberg, Steve Bennett, James E. Smith
1999 — conf
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors.
FTCS
Eric Rotenberg
1999 A* conf
Control Independence in Trace Processors.
MICRO
Eric Rotenberg, James E. Smith
1997 A* conf
Path-Based Next Trace Prediction.
MICRO
Quinn Jacobson, Eric Rotenberg, James E. Smith
1997 A* conf
Trace Processors.
MICRO
Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith
1996 A* conf
Assigning Confidence to Conditional Branch Predictions.
MICRO
Erik Jacobsen, Eric Rotenberg, James E. Smith
1996 A* conf
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching.
MICRO
Eric Rotenberg, Steve Bennett, James E. Smith