Eric Martin - RankMe

77 papers A 5B 1C 9Misc 3Journal 24Unranked 35

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	How Humans Comply With a (Potentially) Faulty Robot: Effects of Multidimensional Transparency. IEEE Trans. Hum. Mach. Syst. Loïck Simon, Clément Guérin, Philippe Rauffet, Christine Chauvin, Eric Martin
2021	—	`conf`	Typology of Manufacturing Digital Twins: A First Step Towards a Deployment Methodology. SOHOMA Nathalie Julien, Eric Martin
2012	—	`conf`	A design approach dedicated to network-based and conflict-free parallel interleavers. ACM Great Lakes Symposium on VLSI Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin
2011	Misc	`conf`	A methodology based on Transportation problem modeling for designing parallel interleaver architectures. ICASSP Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
2011	C	`conf`	An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. ISCAS Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
2010	—	`conf`	Bitwidth-aware high-level synthesis for designing low-power DSP applications. ICECS Ghizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin
2010	—	`conf`	Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. ICECS Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
2010	B	`conf`	Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. FPL Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin
2010	J	`jnl`	Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures CoRR Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard
2010	Misc	`conf`	Static Address Generation Easing: a design methodology for parallel interleaver architectures. ICASSP Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2009	J	`jnl`	Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. J. Signal Process. Syst. Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
2008	J	`jnl`	Estimation et optimisation de la consommation des mémoires. Tech. Sci. Informatiques Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
2007	J	`jnl`	A Design Methodology for Space-Time Adapter CoRR Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	J	`jnl`	A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver CoRR Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	C	`conf`	A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. ISCAS Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	A	`conf`	A design flow dedicated to multi-mode architectures for DSP applications. ICCAD Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
2007	—	`conf`	A design methodology for space-time adapter. ACM Great Lakes Symposium on VLSI Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	J	`jnl`	Application of a design space exploration tool to enhance interleaver generation CoRR Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	—	`conf`	Application of a design space exploration tool to enhance interleaver generation. EUSIPCO Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	—	`conf`	Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system. EUSIPCO Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
2007	J	`jnl`	Constrained algorithmic IP design for system-on-chip. Integr. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
2007	J	`jnl`	Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels CoRR Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	J	`jnl`	Synchronization Processor Synthesis for Latency Insensitive Systems CoRR Pierre Bomel, Eric Martin, Emmanuel Boutillon
2006	J	`jnl`	A Memory Aware High Level Synthesis Too CoRR Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
2006	J	`jnl`	A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
2006	—	`conf`	Design Space Exploration of DSP Applications Based on Behavioral Description Models. SiPS Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
2006	J	`jnl`	Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. Signal Process. Guillaume Savaton, Emmanuel Casseau, Eric Martin
2006	J	`jnl`	G729 Voice Decoder Design. J. VLSI Signal Process. Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin
2006	J	`jnl`	High-level synthesis under I/O Timing and Memory constraints CoRR Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
2006	J	`jnl`	Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power CoRR Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
2006	J	`jnl`	Memory Aware High-Level Synthesis for Embedded Systems CoRR Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
2006	J	`jnl`	Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI CoRR Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin
2005	—	`conf`	A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
2005	—	`conf`	C-based rapid prototyping for digital signal processing. EUSIPCO Emmanuel Casseau, Bertrand Le Gal, Pierre Bomel, Christophe Jégo, Sylvain Huet, Eric Martin
2005	—	`conf`	DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context. SAMOS Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
2005	C	`conf`	High-Level Synthesis in Latency Insensitive System Methodology. DSD Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
2005	—	`conf`	High-level synthesis under I/O timing and memory constraints. ISCAS (1) Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin
2005	—	`conf`	Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. ISVLSI Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin
2005	—	`conf`	Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses. EUSIPCO Bertrand Le Gal, Emmanuel Casseau, Eric Martin
2005	J	`jnl`	SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications. EURASIP J. Adv. Signal Process. Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin
2005	A	`conf`	Synchronization Processor Synthesis for Latency Insensitive Systems. DATE Pierre Bomel, Eric Martin, Emmanuel Boutillon
2005	C	`conf`	SystemCmantic: A high level Modelling and Co-Design Framework. FDL Lobna Kriaa, S. Adriano, Emmanuel Vaumorin, R. Nouacer, F. Blanc, S. Pajaniardja, Philippe Coussy, Eric Martin, Dominique Heller, Farhat Thabet, Anne-Marie Fouilliart
2004	C	`conf`	A Complete Methodology for Memory Optimization in DSP Applications. DSD Florian Marteil, Nathalie Julien, Eric Senn, Eric Martin
2004	—	`conf`	A Memory Aware High Level Synthesis Tool . ISVLSI Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
2004	—	`conf`	A memory aware behavioral synthesis tool for real-time VLSI circuits. ACM Great Lakes Symposium on VLSI Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
2004	—	`conf`	A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder. ICASSP (5) Philippe Coussy, David Gnaedig, Amor Nafkha, Adel Baganne, Emmanuel Boutillon, Eric Martin
2004	A	`conf`	Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors. DATE Johann Laurent, Nathalie Julien, Eric Senn, Eric Martin
2004	C	`conf`	Memory Aware HLS and the Implementation of Ageing Vectors. DSD Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
2004	Misc	`conf`	Memory accesses management during high level synthesis. CODES+ISSS Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin
2004	C	`conf`	Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. DSD David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin
2004	—	`conf`	Reed-Solomon behavioral virtual component for communication systems. ISCAS (4) Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin
2004	—	`conf`	SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. PATMOS Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin
2004	J	`jnl`	Synthèse architecturale d'applications temps réel pour technologies submicroniques. Tech. Sci. Informatiques Emmanuel Casseau, Christophe Jégo, Eric Martin
2004	J	`jnl`	Synthèse d'architecture pour la réalisation comportementale de l'algorithme MAP pour Turbo Décodeur. Ann. des Télécommunications David Gnaedig, Emmanuel Boutillon, Eric Martin, Amor Nafkha, Michel Jézéquel, Jacky Tousch, Nathalie Brengarth
2003	A	`conf`	A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration. DATE Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Riadh Gaiech, Eric Martin
2003	—	`conf`	A simulation based approach for incorporating virtual components IP cores into multimedia systems design. ICASSP (2) Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Eric Martin
2003	A	`conf`	A simulation based approach for incorporating virtual components IP cores into multimedia systems design. ICME Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Eric Martin
2003	C	`conf`	Communication and Timing Constraints Analysis for IP Design and Integration. VLSI-SOC Philippe Coussy, Adel Baganne, Eric Martin
2003	J	`jnl`	Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT. J. VLSI Signal Process. Nathalie Julien, S. Gailhard, Eric Martin
2003	J	`jnl`	Power Consumption Modeling and Characterization of the TI C6201. IEEE Micro Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin
2002	—	`conf`	A design methodology for IP integration. ISCAS (4) Philippe Coussy, Adel Baganne, Eric Martin
2002	—	`conf`	A design methodology for integrating IP into SOC systems. CICC Philippe Coussy, Adel Baganne, Eric Martin
2002	—	`conf`	High-level design verification using Taylor Expansion Diagrams: first results. HLDVT Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin
2002	—	`conf`	IP cores integration in DSP System-on-chip designs. EUSIPCO Philippe Coussy, Adel Baganne, Eric Martin
2002	—	`conf`	Power Consumption Estimation of a C Program for Data-Intensive Applications. PATMOS Eric Senn, Nathalie Julien, Johann Laurent, Eric Martin
2002	—	`conf`	Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor. ISHPC Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin
2002	—	`conf`	Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder. ICECS Philippe Coussy, Adel Baganne, Eric Martin
2001	C	`conf`	A Vision System on Chip for Industrial Control. VLSI-SOC Eric Senn, Eric Martin
2001	—	`conf`	A smart "single line" pixel sensor for industrial vision. ICECS Eric Senn, D. Emzivat, Eric Martin
2001	—	`conf`	Architectural synthesis of digital signal processing applications dedicated to submicron technologies. ICECS Emmanuel Casseau, Christophe Jégo, Eric Martin
1999	J	`jnl`	A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller. J. VLSI Signal Process. Adel Baganne, Jean Luc Philippe, Eric Martin
1999	—	`conf`	Architectural Synthesis with Interconnection Cost Control. VLSI Christophe Jégo, Emmanuel Casseau, Eric Martin
1999	—	`conf`	Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. Great Lakes Symposium on VLSI S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin
1998	—	`conf`	Adaptive filters implementation performances under power dissipation constraint. EUSIPCO Stephane Gailhard, Nathalie Julien, Eric Martin
1998	—	`conf`	How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. Great Lakes Symposium on VLSI S. Gailhard, Nathalie Julien, Jean-Philippe Diguet, Eric Martin
1997	—	`conf`	Hardware interface design for real time embedded systems. Great Lakes Symposium on VLSI Adel Baganne, Jean Luc Philippe, Eric Martin
1993	—	`conf`	GAUT: An architectural synthesis tool for dedicated signal processors. EURO-DAC Eric Martin, Olivier Sentieys, Hélène Dubois, Jean Luc Philippe