Eric Karl

35 papers A* 1Misc 1Journal 13Unranked 20
YearRankTypeTitle / Venue / Authors
2024 — conf
15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia.
ISSCC
Daeyeon Kim, Yusung Kim, Ayush Shrivastava, Gyusung Park, Anandkumar Mahadevan Pillai, Kunal Bannore, Tri Doan, Muktadir Rahman, Gwanghyeon Baek, Clifford Ong, Xiaofei Wang, Zheng Guo, Eric Karl
2024 — conf
An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications.
VLSI Technology and Circuits
Walid M. Hafez, D. Abanulo, M. Abdelkader, S. An, C. Auth, D. Bahr, V. Balakrishnan, Rohan Bambery, M. Beck, M. Bhargava, S. Bhowmick, J. Biggs-houck, J. Birdsall, D. Caselli, H.-Y. Chang, Y. Chang, R. Chaudhuri, S. Chauhan, C. Chen, V. Chikarmane, K. Chikkadi, T. Chu, C. Connor, R. De Alba, Y. Deng, C. Destefano, D. Diana, Y. Dong, P. Elfick, Tyler Elko-Hansen, B. Fallahazad, Y. Fang, D. Gala, D. Garg, C. Geppert, S. Govindaraju, W. Grimm, H. Grunes, L. Guler, Z. Guo, A. Gupta, M. Hattendorf, S. Havelia, J. Hazra, A. Islam, A. Jain, S. Jaloviar, M. Jamil, M. Jang, M. Kabir, J. Kameswaran, Eric Karl, S. Kelgeri, A. Kennedy, C. Kilroy, J. Kim, Y. Kim, D. Krishnan, G. Lee, H.-P. Lee, Q. Li, H. Lin, A. Luk, Y. Luo, P. Macfarlane, A. Mamun, K. Marla, D. Mayeri, Eamonn McKenna, A. Miah, K. Mistry, M. Mleczko, S. Moon, D. Nardi, S. Natarajan, J. Nathawat, C. Nolph, C. Nugroho, P. Nyhus, A. Oni, P. Packan, D. Pak, A. Paliwal, R. Pandey, I. Paredes, K. Park, L. Paulson, A. Pierre, P. Plekhanov, C. Prasad, R. Ramaswamy, J. Riley, Johann Rode, R. Russell, S. Ryu, H. Saavedra, T. Salisbury, Justin Sandford, Faisal Ahmed Shah, K. Shang, P. Shekhar, A. Shu, E. Skoug, J. Sohn, J. Song, M. Sprinkle, J. Su, A. Tan, T. Troeger, R. Tsao, A. Vaidya, C. Wallace, X. Wang, H. Wang, C. Ward, S. Wickramaratne, M. Wills, T. Wu, Z. Xia-hua, S. Xu, P. Yashar, J. Yaung, Y. Yu, M. Zilm, Bernhard Sell
2023 — conf
E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology.
VLSI Technology and Circuits
M. Shamanna, E. Abuayob, G. Aenuganti, C. Alvares, J. Antony, A. Bahudhanam, A. Chandran, P. Chew, A. Chatterjee, B. Chauhan, N. Dandeti, J. Desai, M. Doyle, T. Dmukauskas, P. Farache, E. Fetzer, K. Fischer, P. Hack, Y. Greenzweig, John Giacobbe, Walid M. Hafez, E. Haralson, A. Hegde, A. Illa, M. Islam, S. Jain, M. Jang, J. Nguyen, T. Tong, L. Jiang, Eric Karl, P. Kalangi, G. Khoo, A. Krishnamoorthy, B. Kuns, W. Li, R. Livengood, T. Malik, R. Priyanka, H. Faraby, Y. Maymon, K. Mistry, K. Morgan, S. Natarajan, O. Nevo, M. Oh, P. Pardy, J. Park, P. Penmatsa, Boyd Phelps, C. Peterson, S. Rajappa, A. Raveh, A Rezaie, T. Ravishankar, R. Ramaswamy, S. Reddy, R. Saha, S. Sen, R. Sanchez, R. Sanaga, B. Simkhovich, Bernhard Sell, M. Senger, B. Schnarch, M. Seshadri, O. Sidorov, S. Subramanian, K. Subramanian, B. Truong, S. Bangalore, Jeffery Hicks, S. Venkatesh, D. Christensen, K. Bhargav, M. Von Haartman, P. Joshi, S. Zickel, C.-H. Lin, J. Huening, T.-H. Wu, N. Bakken, A. Afzal, A. Raman, Sj. Rao, V. Kawar, J. Neirynck, D. Bradley, M. Duwe, S. Wu, V. Patil, M. Bayoumy
2023 J jnl
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology.
IEEE J. Solid State Circuits
Yusung Kim, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl
2022 — conf
A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology.
VLSI Technology and Circuits
Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni
2022 — conf
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology.
VLSI Technology and Circuits
Yusung Kim, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl
2022 — conf
Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing.
ISSCC
Wilfred Gomes, Altug Koker, Patrick N. Stover, Doug B. Ingerly, Scott Siers, Srikrishnan Venkataraman, Chris Pelto, Tejas Shah, Amreesh Rao, Frank O'Mahony, Eric Karl, Lance Cheney, Iqbal Rajwani, Hemant Jain, Ryan Cortez, Arun Chandrasekhar, Basavaraj Kanthi, Raja Koduri
2021 J jnl
Advances in Microprocessor Cache Architectures Over the Last 25 Years.
IEEE Micro
Ravi R. Iyer, Vivek De, Ramesh Illikkal, David A. Koufaty, Bhushan Chitlur, Andrew Herdrich, Muhammad M. Khellah, Fatih Hamzaoglu, Eric Karl
2021 — conf
F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets.
ISSCC
Christopher Gonzalez, Huichu Liu, Mijung Noh, Eric Karl, Thomas Toifl, Shawn S. H. Hsu
2021 J jnl
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits
Friedel Gerfers, Ping-Hsuan Hsieh, Dejan Markovic, Jun Deguchi, Eric Karl
2021 Misc conf
Investigating Barriers for the Adoption of the German Contact-Tracing App and the Influence of a Video Intervention on User Acceptance.
MuC
Victoria Böhm, Christian Wolff, Corinna Geiselhart, Eric Karl, Nina Kleindienst
2021 — conf
SE1: What Technologies Will Shape the Future of Computing?
ISSCC
Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag
2021 — conf
Session 24 Overview: Advanced Embedded Memories Memory Subcommittee.
ISSCC
Eric Karl, Shinichiro Shiratake, Jonathan Chang
2020 — conf
A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead.
VLSI Circuits
Zheng Guo, Jami Wiedemer, Yusung Kim, Prithvee Sundararajan Ramamoorthy, Prateeksha Bindiganavile Sathyaprasad, Smita Shridharan, Daeyeon Kim, Eric Karl
2019 J jnl
A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications.
IEEE J. Solid State Circuits
Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl
2018 — conf
A 23.6Mb/mm
ISSCC
Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl
2017 J jnl
5.6 Mb/mm
IEEE J. Solid State Circuits
Jaydeep P. Kulkarni, John Keane, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
2016 — conf
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology.
ISSCC
John Keane, Jaydeep P. Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
2016 J jnl
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry.
IEEE J. Solid State Circuits
Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang
2015 — conf
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology.
ISSCC
Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang
2015 — conf
A 14 nm SoC platform technology featuring 2
VLSIC
Chia-Hong Jan, F. Al-amoody, H.-Y. Chang, T. Chang, Y.-W. Chen, N. Dias, Walid M. Hafez, Doug B. Ingerly, M. Jang, Eric Karl, S. K.-Y. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C.-G. Lee, J. Lee, T. Leo, P.-C. Liu, N. Nidhi, R. Olac-vaw, C. Petersburg, K. Phoa, Chetan Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, Aravinth Subramaniam, C. Tsai, Peter Vandervoorn, L. Yang, A. Zainuddin, Peng Bai
2013 J jnl
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.
IEEE J. Solid State Circuits
Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Mesut Meterelliyoz, John Keane, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr
2012 — conf
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry.
ISSCC
Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr
2012 J jnl
Compact Degradation Sensors for Monitoring NBTI and Oxide Degradation.
IEEE Trans. Very Large Scale Integr. Syst.
Prashant Singh, Eric Karl, David T. Blaauw, Dennis Sylvester
2011 J jnl
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation.
IEEE J. Solid State Circuits
Pramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang, Kevin Zhang
2011 J jnl
Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap.
Prashant Singh, Eric Karl, Dennis Sylvester, David T. Blaauw
2010 — conf
A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation.
ISSCC
Hyunwoo Nho, Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric Karl, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang
2010 — conf
Dynamic NBTI management using a 45nm multi-degradation sensor.
CICC
Prashant Singh, Eric Karl, Dennis Sylvester, David T. Blaauw
2009 J jnl
Sensor-Driven Reliability and Wearout Management.
IEEE Des. Test Comput.
Prashant Singh, Cheng Zhuo, Eric Karl, David T. Blaauw, Dennis Sylvester
2008 — conf
Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures.
ISQED
Eric Karl, Dennis Sylvester, David T. Blaauw
2008 — conf
Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation.
ISSCC
Eric Karl, Prashant Singh, David T. Blaauw, Dennis Sylvester
2008 J jnl
Multi-Mechanism Reliability Modeling and Management in Dynamic Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Eric Karl, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge
2006 J jnl
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon.
IEEE Des. Test Comput.
Dennis Sylvester, David T. Blaauw, Eric Karl
2006 A* conf
Reliability modeling and management in dynamic microprocessor-based systems.
DAC
Eric Karl, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge
2005 — conf
Timing error correction techniques for voltage-scalable on-chip memories.
ISCAS (4)
Eric Karl, Dennis Sylvester, David T. Blaauw