Eric Guthmuller

18 papers A 3C 3Journal 3Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Hardware Accelerator for the Goemans-Williamson Algorithm.
CoRR
David A. Herrera-Martí, Eric Guthmuller, Jérôme Fereyre
2024 A conf
A Scalable Low-Latency FPGA Architecture for Spin Qubit Control Through Direct Digital Synthesis.
DATE
Mathieu Toubeix, Eric Guthmuller, Adrian Evans, Tristan Meunier
2024 — conf
A Variable and Extended Precision (VRP) Accelerator and its 22 nm SoC Implementation.
DCIS
César Fuguet, Eric Guthmuller, Andrea Bocco, Jérôme Fereyre, Adrian Evans, Yves Durand
2024 J jnl
Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation.
IEEE Trans. Computers
Eric Guthmuller, César Fuguet, Andrea Bocco, Jérôme Fereyre, Riccardo Alidori, Ihsane Tahir, Yves Durand
2022 C conf
Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor.
ARITH
Yves Durand, Eric Guthmuller, César Fuguet Tortolero, Jérôme Fereyre, Andrea Bocco, Riccardo Alidori
2021 J jnl
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits
Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
2021 A conf
Storage Class Memory with Computing Row Buffer: A Design Space Exploration.
DATE
Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal
2020 — conf
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm
ISSCC
Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
2018 — conf
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.
ESSCIRC
Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet
2018 — conf
Dynamic Coherent Cluster: A Scalable Sharing Set Management Approach.
ASAP
Julie Dumas, Eric Guthmuller, Frédéric Pétrot
2017 — conf
A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols.
ARCS
Julie Dumas, Eric Guthmuller, César Fuguet Tortolero, Frédéric Pétrot
2017 — conf
Trace-driven exploration of sharing set management strategies for cache coherence in manycores.
NEWCAS
Julie Dumas, Eric Guthmuller, César Fuguet Tortolero, Frédéric Pétrot
2015 — conf
3D advanced integration technology for heterogeneous systems.
3DIC
Pascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Gaël Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy
2015 — conf
Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects.
ISVLSI
Pascal Vivet, Christian Bernard, Eric Guthmuller, Ivan Miro Panades, Yvain Thonnart, Fabien Clermidy
2013 A conf
3D integration for power-efficient computing.
DATE
Denis Dutoit, Eric Guthmuller, Ivan Miro Panades
2013 C conf
3D stacking for multi-core architectures: From WIDEIO to distributed caches.
ISCAS
Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Pascal Vivet
2013 C conf
Architectural exploration of a fine-grained 3D cache for high performance in a manycore context.
VLSI-SoC
Eric Guthmuller, Ivan Miro Panades, Alain Greiner
2012 — conf
Adaptive Stackable 3D Cache Architecture for Manycores.
ISVLSI
Eric Guthmuller, Ivan Miro Panades, Alain Greiner