Eric Faehn - RankMe

18 papers A 5B 2C 4Misc 1Journal 2Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A Digital SRAM Modeling for Cell-Aware Testing and Test Algorithms Evaluation. IOLTS D. Ronga, Xhesila Xhafa, Eric Faehn, Patrick Girard, T. Vayssade, Arnaud Virazel
2025	C	`conf`	A Runtime Efficient Graph-Based Cell-Aware Model Generation for Structural SRAM Testing. IOLTS Gianmarco Mongelli, Xhesila Xhafa, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2025	A	`conf`	Accelerating Cell-Aware Model Generation for Sequential Cells using Graph Theory. DATE Gianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2025	—	`conf`	Memory Dynamic Faults and Array-Level Faults Detector in Digital Test Environment. DFT D. Ronga, Eric Faehn, Patrick Girard, Arnaud Virazel
2025	J	`jnl`	SRAM Periphery Testing Using the Cell-Aware Test Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xhesila Xhafa, Eric Faehn, Patrick Girard, Arnaud Virazel
2024	A	`conf`	A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation. ITC Gianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2024	C	`conf`	A Graph-Based Methodology for Speeding up Cell-Aware Model Generation. IOLTS Gianmarco Mongelli, Xhesila Xhafa, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2024	—	`conf`	A Structural Testing Approach for SRAM Address Decoders Using Cell-Aware Methodology. DFT Xhesila Xhafa, Eric Faehn, Patrick Girard, Arnaud Virazel
2024	—	`conf`	Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM. DTTIS D. Ronga, Xhesila Xhafa, Eric Faehn, Patrick Girard, Thibault Vayssade, Arnaud Virazel
2023	B	`conf`	On Using Cell-Aware Methodology for SRAM Bit Cell Testing. ETS Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory di Pendina, Patrick Girard, Arnaud Virazel
2022	A	`conf`	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure. ITC Michele Portolan, Antonios Pavlidis, Giorgio Di Natale, Eric Faehn, Haralampos-G. Stratigopoulos
2022	Misc	`conf`	Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs. VTS Antonios Pavlidis, Eric Faehn, Marie-Minerve Louërat, Haralampos-G. Stratigopoulos
2021	B	`conf`	BIST-Assisted Analog Fault Diagnosis. ETS Antonios Pavlidis, Eric Faehn, Marie-Minerve Louërat, Haralampos-G. Stratigopoulos
2021	J	`jnl`	SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety. IEEE Trans. Circuits Syst. I Regul. Pap. Antonios Pavlidis, Marie-Minerve Louërat, Eric Faehn, Anand Kumar, Haralampos-G. Stratigopoulos
2020	A	`conf`	Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP. DATE Antonios Pavlidis, Marie-Minerve Louërat, Eric Faehn, Anand Kumar, Haralampos-G. D. Stratigopoulos
2019	C	`conf`	Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. IOLTS Safa Mhamdi, Arnaud Virazel, Patrick Girard, Alberto Bosio, Etienne Auvray, Eric Faehn, Aymen Ladhar
2018	A	`conf`	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. ITC Tien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick Girard
2012	—	`conf`	A Hybrid Flow for Memory Failure Bitmap Classification. Asian Test Symposium Jianbo Li, Yu Huang, Wu-Tung Cheng, Chris Schuermyer, Dong Xiang, Eric Faehn, Ruth Farrugia