Erfan Azarkhish

16 papers A 1Journal 8Unranked 6
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs.
ACM Trans. Embed. Comput. Syst.
Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini
2021 J jnl
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs.
CoRR
Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini
2021 — conf
A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge.
VLSI Circuits
Petar Jokic, Erfan Azarkhish, Régis Cattenoz, Engin Türetken, Luca Benini, Stéphane Emery
2021 — conf
Single-Battery Cooperative Sensors For Multi-Lead Long Term Ambulatory ECG Measurement.
BioCAS
Komail M. H. Badami, Marc Pons Solé, Erfan Azarkhish, André Fivaz, Michaël Rapin, Olivier Chételat, Stéphane Emery
2019 — conf
A 20 Channel EMG SoC with an Integrated 32b RISC Core for Real-Time Wireless Prosthetic Control.
ESSCIRC
Marc Pons Solé, Andre Bischof, Lorenzo Bergamini, Philippe Dallemagne, Stéphane Emery, Komail M. H. Badami, Jiang Deng, Themistoklis Mavrogordatos, Erfan Azarkhish, Loïc Zahnd, Costantino Cosentino, Marcin K. Augustyniak, Yingyun Zha
2018 J jnl
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes.
IEEE Trans. Parallel Distributed Syst.
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2017 J jnl
A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters.
IEEE Embed. Syst. Lett.
Maryam Payami, Erfan Azarkhish, Igor Loi, Luca Benini
2017 J jnl
Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube.
IEEE Trans. Very Large Scale Integr. Syst.
Erfan Azarkhish, Christoph Pfister, Davide Rossi, Igor Loi, Luca Benini
2017 J jnl
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes.
CoRR
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2016 — conf
Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube.
ARCS
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2016 — —
Memory Hierarchy Design for Next Generation Scalable Many-core Platforms.
Erfan Azarkhish
2015 J jnl
A Modular Shared L2 Memory Design for 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst.
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2015 A conf
High performance AXI-4.0 based interconnect for extensible smart memory cubes.
DATE
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2013 — conf
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters.
NOCS
Erfan Azarkhish, Igor Loi, Luca Benini
2013 J jnl
A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects.
IET Comput. Digit. Tech.
Erfan Azarkhish, Igor Loi, Luca Benini
2013 — conf
A high-performance multiported L2 memory IP for scalable three-dimensional integration.
3DIC
Erfan Azarkhish, Igor Loi, Luca Benini