Erdal Oruklu - RankMe

60 papers C 5Misc 2Journal 20Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Parallel Sort Implementation and Evaluation in a Dataflow-Based Polymorphic Computing Architecture. Comput. David Hentrich, Erdal Oruklu, Jafar Saniie
2024	J	`jnl`	Accelerating a Meta Learning Model for Ultrasonic Non-Destructive Testing Applications Using Model Compression and FPGA Hardware. J. Signal Process. Syst. Yu Yuan, Kushal Virupakshappa, Erdal Oruklu
2022	J	`jnl`	FPGA Implementation of an Ultrasonic Flaw Detection Algorithm Based on Convolutional Neural Networks. J. Signal Process. Syst. Yu Yuan, Kushal Virupakshappa, Erdal Oruklu
2022	—	`conf`	Hardware Efficient Implementation of an Ultrasonic Non-Destructive Evaluation Algorithm based on DeepLearning. MWSCAS Yu Yuan, Kushal Virupakshappa, Erdal Oruklu
2021	J	`jnl`	Program diagramming and fundamental programming patterns for a polymorphic computing dataflow processor. J. Comput. Lang. David Hentrich, Erdal Oruklu, Jafar Saniie
2020	C	`conf`	Fine-Grained Instruction Placement in Polymorphic Computing Architectures. ISCAS David Hentrich, Erdal Oruklu, Jafar Saniie
2019	Misc	`conf`	From Design to Implementation - Algorithm Conversion and Transition to a Mobile Platform for an Artificial Pancreas. SIGITE Caterina Lazaro Martinez, Erdal Oruklu, Mudassir M. Rashid, Mert Sevil, Iman Hajizadeh, Ali Cinar, Jeremy R. Hajek
2019	—	`conf`	Investigation of Feature Inputs for Binary Classification of Ultrasonic NDT Signals using SVM and Neural Networks. MWSCAS Kushal Virupakshappa, Erdal Oruklu
2019	—	`conf`	Side-Channel Attack Resilient Design of a 10T SRAM Cell in 7nm FinFET Technology. MWSCAS Kangqi Chen, Erdal Oruklu
2018	J	`jnl`	A Dataflow Processor as the Basis of a Tiled Polymorphic Computing Architecture with Fine-Grain Instruction Migration. IEEE Trans. Parallel Distributed Syst. David Hentrich, Erdal Oruklu, Jafar Saniie
2018	—	`conf`	Full Adder Circuit Design Using Lateral Gate-All-Around (LGAA) FETs Based on BSIM-CMG Mode. MWSCAS Muyu Yang, Erdal Oruklu
2017	—	`conf`	FPGA implementation of a support vector machine classifier for Ultrasonic flaw detection. MWSCAS Yiyue Jiang, Kushal Virupakshappa, Erdal Oruklu
2017	J	`jnl`	Hardware and Software Implementation of an Artificial Pancreas System on a Mobile Device. IJHCR Caterina Lazaro Martinez, Erdal Oruklu, Mert Sevil, Kamuran Turksoy, Ali Cinar
2017	—	`conf`	Security challenges and solutions for closed-loop artificial pancreas systems. MWSCAS Caterina Lazaro Martinez, Erdal Oruklu, Ali Cinar
2017	—	`conf`	Traffic sign recognition based on the NVIDIA Jetson TX1 embedded system using convolutional neural networks. MWSCAS Yan Han, Erdal Oruklu
2016	—	`conf`	Communication challenges in a multi-sensor closed-loop artificial pancreas system. Wireless Health Caterina Lazaro Martinez, Erdal Oruklu, Mert Sevil, Kamuran Turksoy, Ali Cinar
2016	—	`conf`	Implementation of an artificial pancreas system on a mobile device. EIT Caterina Lazaro Martinez, Erdal Oruklu, Mert Sevil, Kamuran Turksoy, Ali Cinar
2016	—	`conf`	Leakage reduction techniques for FinFET datapath circuits. EIT Yu Yuan, Erdal Oruklu
2015	J	`jnl`	Cyber-Physical Platform Development for Multivariable Artificial Pancreas Systems. Int. J. Handheld Comput. Res. Caterina Lazaro Martinez, Erdal Oruklu, Ali Cinar
2015	—	`conf`	Robust traffic sign recognition with feature extraction and k-NN classification methods. EIT Yan Han, Kushal Virupakshappa, Erdal Oruklu
2015	—	`conf`	Sensor fusion and distributed platform development for artificial pancreas. EIT Caterina Lazaro Martinez, Erdal Oruklu, Ali Cinar
2015	—	`conf`	Standard cell library characterization for FinFET transistors using BSIM-CMG models. EIT Yu Yuan, Cecilia García Martin, Erdal Oruklu
2015	—	`conf`	Traffic sign recognition based on prevailing bag of visual words representation on feature descriptors. EIT Kushal Virupakshappa, Yan Han, Erdal Oruklu
2014	—	`conf`	Leakage power reduction in data driven dynamic logic circuits. EIT Cecilia García Martin, Erdal Oruklu
2014	—	`conf`	Performance evaluation of FinFET pass-transistor full adders with BSIM-CMG model. MWSCAS Cecilia García Martin, Erdal Oruklu
2014	—	`conf`	Performance evaluation of multi-gate fets using the BSIM-CMG model. EIT Neelam Patil, Cecilia García Martin, Erdal Oruklu
2014	—	`conf`	Real-time traffic sign recognition based on Zynq FPGA and ARM SoCs. EIT Yan Han, Erdal Oruklu
2013	—	`conf`	Improved time-frequency distribution using singular value decomposition of Choi-Williams distribution. EIT Juan Lu, Erdal Oruklu, Jafar Saniie
2012	—	`conf`	3D image reconstruction and human body tracking using stereo vision and Kinect technology. EIT Weidi Jia, Won-Jae Yi, Jafar Saniie, Erdal Oruklu
2012	—	`conf`	A high-level synthesis and verification tool for fixed to floating point conversion. MWSCAS Semih Aslan, Erdal Oruklu, Jafar Saniie
2012	—	`conf`	Acoustic sensor array for determination of undersea acoustic signatures. EIT Tom Chu, Jafar Saniie, Erdal Oruklu
2012	J	`jnl`	Image and video processing platform for field programmable gate arrays using a high-level synthesis. IET Comput. Digit. Tech. Christophe Desmouliers, Erdal Oruklu, Semih Aslan, Jafar Saniie, Fernando Martinez-Vallina
2012	—	`conf`	Image processing design flow for virtual fitting room applications used in mobile devices. EIT Cecilia García Martin, Nicolas Bessou, Anne Chadoeuf, Erdal Oruklu
2012	—	`conf`	Real-time traffic sign detection and recognition for in-car driver assistance systems. MWSCAS Erdal Oruklu, Damien Pesty, Joana Neveux, Jean-Emmanuel Guebey
2012	J	`jnl`	Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors. J. Signal Process. Syst. Erdal Oruklu, Xin Xiao, Jafar Saniie
2012	J	`jnl`	Security Policy Management Process within Six Sigma Framework. J. Information Security Vijay Anand, Jafar Saniie, Erdal Oruklu
2012	J	`jnl`	System-on-Chip Subband Decomposition Architectures for Ultrasonic Detection Applications. J. Signal Process. Syst. Erdal Oruklu, Joshua Weber, Jafar Saniie
2011	J	`jnl`	Direction of Arrival Estimation and Localization Using Acoustic Sensor Arrays. J. Sens. Technol. Vitaliy Kunin, Marcos Turqueti, Jafar Saniie, Erdal Oruklu
2011	J	`jnl`	Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s. IET Circuits Devices Syst. Christophe Desmouliers, Erdal Oruklu, Jafar Saniie
2011	J	`jnl`	FPGA-Based Configurable Frequency-Diverse Ultrasonic Target-Detection System. IEEE Trans. Ind. Electron. Joshua Weber, Erdal Oruklu, Jafar Saniie
2011	J	`jnl`	Fast Signed-Digit Multi-operand Decimal Adders. Circuits Syst. Jeff Rebacz, Erdal Oruklu, Jafar Saniie
2011	J	`jnl`	Polymorphic Computing: Definition, Trends, and a New Agent-Based Architecture. Circuits Syst. David Hentrich, Erdal Oruklu, Jafar Saniie
2011	Misc	`conf`	Trusted computing architectures for a mobile IT infrastructure. SIGUCCS Vijay Anand, Jafar Saniie, Erdal Oruklu
2010	J	`jnl`	Constant addition with flagged binary adder architectures. Integr. Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie
2010	C	`conf`	Reduced memory architecture for CORDIC-based FFT. ISCAS Xin Xiao, Erdal Oruklu, Jafar Saniie
2009	J	`jnl`	Dynamically Reconfigurable Architecture Design for Ultrasonic Imaging. IEEE Trans. Instrum. Meas. Erdal Oruklu, Jafar Saniie
2009	—	`conf`	FPGA-based design of a high-performance and modular video processing platform. EIT Christophe Desmouliers, Erdal Oruklu, Jafar Saniie
2009	—	`conf`	Fast memory addressing scheme for radix-4 FFT implementation. EIT Xin Xiao, Erdal Oruklu, Jafar Saniie
2009	—	`conf`	High performance signed-digit decimal adders. EIT Jeff Rebacz, Erdal Oruklu, Jafar Saniie
2009	—	`conf`	Performance evaluation of SRAM cells in 22nm predictive CMOS technology. EIT David Hentrich, Erdal Oruklu, Jafar Saniie
2009	—	`conf`	Realization of area efficient QR factorization using unified division, square root, and inverse square root hardware. EIT Semih Aslan, Erdal Oruklu, Jafar Saniie
2008	J	`jnl`	An Efficient FFT Engine With Reduced Addressing Logic. IEEE Trans. Circuits Syst. II Express Briefs Xin Xiao, Erdal Oruklu, Jafar Saniie
2008	J	`jnl`	Fast Chirplet Transform With FPGA-Based Implementation. IEEE Signal Process. Lett. Yufeng Lu, Erdal Oruklu, Jafar Saniie
2008	—	`conf`	Fpga-based hardware/software co-design for chirplet signal decomposition. ACM Great Lakes Symposium on VLSI Yufeng Lu, Erdal Oruklu, Jafar Saniie
2008	C	`conf`	Performance analysis of flagged prefix adders with logical effort. ISCAS Erdal Oruklu, Vibhuti B. Dave, Jafar Saniie
2008	—	`conf`	Universal Wavelet Kernel Implementation Using Reconfigurable Hardware. ReConFig Christophe Desmouliers, Erdal Oruklu, Jafar Saniie
2007	C	`conf`	Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder. ISCAS John Moskal, Erdal Oruklu, Jafar Saniie
2007	C	`conf`	Design and Synthesis of a Three Input Flagged Prefix Adder. ISCAS Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie
2005	—	`conf`	Reconfigurable architecture for ultrasonic signal compression and target detection. ICASSP (5) Erdal Oruklu, Guilherme Cardoso, Jafar Saniie
2004	—	`conf`	Multiplierless architectures for frequency-diverse target detection algorithms. Circuits, Signals, and Systems Erdal Oruklu, Jafar Saniie