Enrique San Millán

26 papers A 3C 8Journal 9Unranked 6
YearRankTypeTitle / Venue / Authors
2023 J jnl
Time Synchronization Technique Hardware Implementation for OFDM Systems With Hermitian Symmetry for VLC Applications.
IEEE Access
Randy Lozada Dominguez, Juan Sebastián Betancourt Perlaza, Enrique San Millán
2021 J jnl
Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC.
J. Supercomput.
Jose A. Belloch, Germán León, José M. Badía, Almudena Lindoso, Enrique San Millán
2018 J jnl
Dynamic control of entropy and power consumption in TRNGs for IoT applications.
IEICE Electron. Express
Honorio Martín, Enrique San Millán, Luis Entrena-Arrontes
2017 J jnl
A lightweight implementation of the Tav-128 hash function.
IEICE Electron. Express
Honorio Martín, Pedro Peris-López, Enrique San Millán, Juan E. Tapiador
2016 J jnl
A New TRNG Based on Coherent Sampling With Self-Timed Rings.
IEEE Trans. Ind. Informatics
Honorio Martín, Pedro Peris-Lopez, Juan E. Tapiador, Enrique San Millán
2015 J jnl
Fault Attacks on STRNGs: Impact of Glitches, Temperature, and Underpowering on Randomness.
IEEE Trans. Inf. Forensics Secur.
Honorio Martín, Thomas Korak, Enrique San Millán, Michael Hutter
2014 J jnl
An Estimator for the ASIC Footprint Area of Lightweight Cryptographic Algorithms.
IEEE Trans. Ind. Informatics
Honorio Martín, Pedro Peris-Lopez, Juan E. Tapiador, Enrique San Millán
2014 C conf
Effect of ionizing radiation on TRNGs for safe telecommunications: Robustness and randomness.
IOLTS
Honorio Martín, Anna Vaskova, Celia López-Ongil, Enrique San Millán, Marta Portela-García
2011 C conf
AKARI-X: A pseudorandom number generator for secure lightweight systems.
IOLTS
Honorio Martín, Enrique San Millán, Luis Entrena, Julio César Hernández Castro, Pedro Peris-Lopez
2011 C conf
Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness.
IOLTS
Anna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena
2010 — conf
Cryptographically secure pseudo-random bit generator for RFID tags.
ICITST
Pedro Peris-Lopez, Enrique San Millán, Jan C. A. van der Lubbe, Luis Entrena
2010 C conf
Robust cryptographic ciphers with on-line statistical properties validation.
IOLTS
Anna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena
2009 C conf
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers.
IOLTS
Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena
2009 — conf
Security Flaws in an Efficient Pseudo-Random Number Generator for Low-Power Environments.
SEWCN
Pedro Peris-Lopez, Julio C. Hernandez-Castro, Juan M. Estévez-Tapiador, Enrique San Millán, Jan C. A. van der Lubbe
2008 C conf
Logic Transformations by Multiple Wire Network Addition.
DSD
Enrique San Millán, Luis Entrena, José Alberto Espejo
2008 C conf
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard.
IOLTS
Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena
2007 — conf
Correlation-Based Fingerprint Matching with Orientation Field Alignment.
ICB
Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán
2007 J jnl
Low power data processing system with self-reconfigurable architecture.
J. Syst. Archit.
Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena
2003 J jnl
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques.
J. Syst. Archit.
Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López
2001 — conf
Functional extension of structural logic optimization techniques.
ASP-DAC
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
2001 A conf
Generalized reasoning scheme for redundancy addition and removal logic optimization.
DATE
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
2001 — conf
Logic Optimization of Unidirectional Circuits with Structural Methods.
IOLTW
Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo
2001 A conf
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits.
ICCAD
Enrique San Millán, Luis Entrena, José Alberto Espejo
2001 C conf
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization.
DSD
Enrique San Millán, Luis Entrena, José Alberto Espejo
1999 A conf
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization.
DATE
Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno
1999 — conf
Logic Restructuring for MUX-Based FPGAs.
EUROMICRO
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías