Enrique Ostúa

15 papers C 1Journal 7Unranked 7

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Address-encoded byte order. Microprocess. Microsystems David Guerrero Martos, German Cano-Quiveu, Jorge Juan-Chico, Alejandro Millán, Manuel J. Bellido, Julian Viejo, Paulino Ruiz-de-Clavijo, Enrique Ostúa
2020	J	`jnl`	Using the complement of the cosine to compute trigonometric functions. EURASIP J. Adv. Signal Process. David Guerrero Martos, Alejandro Millán Calderón, Jorge Juan-Chico, Julian Viejo, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa
2017	J	`jnl`	Minimalistic SDHC-SPI hardware reader module for boot loader applications. Microelectron. J. Paulino Ruiz-de-Clavijo, Enrique Ostúa, Manuel Jesús Bellido Díaz, Jorge Juan, Julian Viejo, David Guerrero Martos
2012	J	`jnl`	Long-term on-chip verification of systems with logical events scattered in time. Microprocess. Microsystems Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Enrique Ostúa, Juan Quiros
2011	J	`jnl`	Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
2010	—	`conf`	Design and implementation of a suitable core for on-chip long-term verification. SIES Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa
2007	—	`conf`	Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz
2007	J	`jnl`	Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electron. David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
2007	—	`conf`	Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
2006	J	`jnl`	Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electron. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa, Julian Viejo
2006	C	`conf`	Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos
2005	—	`conf`	Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo
2005	—	`conf`	Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo
2004	—	`conf`	Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
2003	—	`conf`	Internode: Internal Node Logic Computational Model. Annual Simulation Symposium Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Enrique Ostúa