Enrico Temporiti

28 papers C 1Journal 10Unranked 17

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	23.2 A 2-Channel 800Gb/s Transceiver for Coherent-Lite Applications with <300ns Latency in 5nm FinFET. ISSCC Marco Sosio, Claudio Nani, Enrico Monaco, Nicola Ghittori, Domenico Albano, Alessio Di Pasquo, Alessandro Bosi, Travis Lovitt, Gabriele Gira, Fulvio Martinelli, Victor Karam, Devrishi Khanna, Mehdi N. Khiarak, Sasan Cyrusian, Mehdi Davoodi, Marco Garampazzi, Nimesh N. Miral, Fabio Giunco, Ivan Fabiano, Nicola Codega, Claudio Asero, Leonardo Daniel Herbas Burgos, Enrico Temporiti, Shawn Scouten, Kishore Kota, Yang Fu, Ruibin Jin, Josef Mueller, Michael Leung, Arash Farhoodfar, Stephen Jantzi, Ken Chang
2025	J	`jnl`	A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz. IEEE J. Solid State Circuits Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi
2025	J	`jnl`	An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process. IEEE J. Solid State Circuits Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, Travis Lovitt, Victor Karam, Domenico Albano, Claudio Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, Leonardo Daniel Herbas Burgos, Stanley S. K. Ho, Enrico Monaco, Benjamín T. Reyes, Paolo Rossi, Enrico Temporiti, Paolo Pascale, Fernando De Bernardinis, Shawn Scouten, Stephen Jantzi
2024	—	`conf`	A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. VLSI Technology and Circuits Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi
2019	—	`conf`	A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With - 15.2-dBm OMA Sensitivity. ESSCIRC Farhad Bozorgi, Melchiorre Bruccoleri, Matteo Repossi, Enrico Temporiti, Andrea Mazzanti, Francesco Svelto
2019	J	`jnl`	A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS. IEEE J. Solid State Circuits Emanuele Depaoli, Hongyang Zhang, Marco Mazzini, Walter Audoglio, Augusto Andrea Rossi, Guido Albasini, Massimo Pozzoni, Simone Erba, Enrico Temporiti, Andrea Mazzanti
2016	—	`conf`	23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies. ISSCC Enrico Temporiti, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Andrea Ghilioni, Francesco Svelto
2016	C	`conf`	A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links. ISCAS Dan Li, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Andrea Ghilioni, Enrico Temporiti, Francesco Svelto
2016	J	`jnl`	Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures. IEEE J. Solid State Circuits Enrico Temporiti, Andrea Ghilioni, Gabriele Minoia, Piero Orlandi, Matteo Repossi, Daniele Baldi, Francesco Svelto
2015	—	`conf`	22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s. ISSCC Marco Cignoli, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Andrea Ghilioni, Enrico Temporiti, Francesco Svelto
2015	—	`conf`	Power consumption estimation for the silicon-photonics reflective ONU conceived within the FABULOUS European project. ICTON Silvio Abrate, Roberto Gaudino, Benoît Charbonnier, Sylvie Menezo, Enrico Temporiti, Guang-Hua Duan, Peter O'Brien, Guido Giuliani
2015	—	`conf`	Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform. OFC Frédéric Boeuf, Sebastien Cremer, Enrico Temporiti, Massimo Fere, Mark Shaw, Nathalie Vulliet, Bastien Orlando, Delia Ristoiu, Alexis Farcy, Thierry Pinguet, Attila Mekis, Gianlorenzo Masini, Peng Sun, Yuemeng Chi, Herve Petiton, Sebastien Jan, Jean-Robert Manouvrier, Charles Baudot, Patrick Le Maitre, Jean Francois Carpentier, Laurent Salager, Matteo Traldi, Luca Maggi, Danilo Rigamonti, Chiara Zaccherini, Carolina Elemi, Bernard Sautreuil, Luigi Verga
2015	—	`conf`	Silicon photonics and FDMA-PON: Insights from the EU FP7 FABULOUS project. OFC Silvio Abrate, Roberto Gaudino, Guido Giuliani, Enrico Temporiti, Peter O'Brien, Guang-Hua Duan, Sylvie Menezo, Benoît Charbonnier
2014	—	`conf`	A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies. ESSCIRC Enrico Temporiti, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Andrea Ghilioni, Francesco Svelto
2014	—	`conf`	A 5 ESSCIRC Nicolo Sabatino, Gabriele Minoia, M. Roche, Daniele Baldi, Enrico Temporiti, Andrea Mazzanti
2014	J	`jnl`	A Low-Noise Design Technique for High-Speed CMOS Optical Receivers. IEEE J. Solid State Circuits Dan Li, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Enrico Temporiti, Andrea Mazzanti, Francesco Svelto
2014	—	`conf`	FDMA-PON and NG-PON2: Performance and cost comparison. ICTON Silvio Abrate, Roberto Gaudino, Benoît Charbonnier, Sylvie Menezo, Enrico Temporiti, Guang-Hua Duan, Peter O'Brien
2012	—	`conf`	A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4. ESSCIRC Dan Li, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Enrico Temporiti, Andrea Mazzanti, Francesco Svelto
2011	J	`jnl`	A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS. IEEE J. Solid State Circuits Federico Vecchi, Stefano Bozzola, Enrico Temporiti, Davide Guermandi, Massimo Pozzoni, Matteo Repossi, Marco Cusmai, Ugo Decanis, Andrea Mazzanti, Francesco Svelto
2010	J	`jnl`	A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation. IEEE J. Solid State Circuits Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Marco Cusmai, Francesco Svelto
2010	—	`conf`	A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation. ISSCC Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Marco Cusmai, Francesco Svelto
2010	—	`conf`	A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators. ISSCC Federico Vecchi, Stefano Bozzola, Massimo Pozzoni, Davide Guermandi, Enrico Temporiti, Matteo Repossi, Ugo Decanis, Andrea Mazzanti, Francesco Svelto
2010	J	`jnl`	Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs. IEEE Trans. Circuits Syst. I Regul. Pap. Colin Weltin-Wu, Enrico Temporiti, Marco Cusmai, Daniele Baldi, Francesco Svelto
2009	J	`jnl`	A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. IEEE J. Solid State Circuits Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto
2009	—	`conf`	Insights into wideband fractional All-Digital PLLs for RF applications. CICC Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto
2008	—	`conf`	A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction. ISSCC Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Francesco Svelto
2004	J	`jnl`	A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications. IEEE J. Solid State Circuits Enrico Temporiti, Guido Albasini, Ivan Bietti, Rinaldo Castello, Matteo Colombo
2003	—	`conf`	An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques. CICC Ivan Bietti, Enrico Temporiti, Guido Albasini, Rinaldo Castello