Enric Musoll - RankMe

20 papers A* 1A 1C 1Journal 10Unranked 7

Year	Rank	Type	Title / Venue / Authors
2011	J	`jnl`	Variable-size mosaics: A process-variation aware technique to increase the performance of tile-based, massive multi-core processors. Comput. Electr. Eng. Enric Musoll
2010	J	`jnl`	A cost-effective load-balancing policy for tile-based, massive multi-core packet processors. ACM Trans. Embed. Comput. Syst. Enric Musoll
2010	J	`jnl`	Hardware-Based Load Balancing for Massive Multicore Architectures Implementing Power Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Enric Musoll
2010	—	`conf`	Load balancing packets on a tile-based massive multi-core processor with S-NUCA. ANCS Enric Musoll
2009	J	`jnl`	A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors. IEEE Comput. Archit. Lett. Enric Musoll
2009	J	`jnl`	Leakage-saving opportunities in mesh-based massive multi-core architectures. SIGARCH Comput. Archit. News Enric Musoll
2009	J	`jnl`	Mesh-based many-core performance under process variations: a core yield perspective. SIGARCH Comput. Archit. News Enric Musoll
2009	—	`conf`	Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures. ISQED Enric Musoll
2008	—	`conf`	A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors. ISQED Enric Musoll
2008	—	`conf`	Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating. SASP Enric Musoll
2008	J	`jnl`	Power Gating Clustered Many-Core Architectures. J. Low Power Electron. Enric Musoll
2003	J	`jnl`	Speculating to reduce unnecessary power consumption. ACM Trans. Embed. Comput. Syst. Enric Musoll
1999	A*	`conf`	Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors. MICRO Enric Musoll
1998	C	`conf`	Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus. ICCD Tomás Lang, Enric Musoll, Jordi Cortadella
1998	J	`jnl`	Register-Transfer Level Transformations for Low-Power Data-Paths. Integr. Comput. Aided Eng. Enric Musoll, Jordi Cortadella
1998	J	`jnl`	Working-zone encoding for reducing the energy in microprocessor address buses. IEEE Trans. Very Large Scale Integr. Syst. Enric Musoll, Tomás Lang, Jordi Cortadella
1997	A	`conf`	Exploiting the locality of memory references to reduce the address bus energy. ISLPED Enric Musoll, Tomás Lang, Jordi Cortadella
1996	—	`conf`	Optimizing CMOS Circuits for Low Power Using Transistor Reordering. ED&TC Enric Musoll, Jordi Cortadella
1995	—	`conf`	High-level synthesis techniques for reducing the activity of functional units. ISLPD Enric Musoll, Jordi Cortadella
1995	—	`conf`	Scheduling and resource binding for low power. ISSS Enric Musoll, Jordi Cortadella