Endri Bezati - RankMe

53 papers A 2B 3C 3Misc 10Journal 11Unranked 23

Year	Rank	Type	Title / Venue / Authors
2025	B	`conf`	Optimal tables for asymmetric numeral systems. ITW Raphael S. Steiner, Mirko De Vita, Endri Bezati
2025	J	`jnl`	Optimal tables for asymmetric numeral systems. CoRR Raphael S. Steiner, Mirko De Vita, Endri Bezati
2023	—	`conf`	ART: An Actor transition systems RunTime for enabling efficient partitioning of neural network graphs. CODAI Endri Bezati
2022	B	`conf`	Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks. PACT Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus
2021	—	`conf`	Generating hardware and software for RISC-V cores generated with Rocket Chip generator. SoCC Süleyman Savas, Endri Bezati, Jörn W. Janneck
2021	J	`jnl`	StreamBlocks: A compiler for heterogeneous dataflow computing (technical report). CoRR Endri Bezati, Mahyar Emami, Jörn W. Janneck, James R. Larus
2021	A	`conf`	Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems. FPGA Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus
2020	A	`conf`	Advanced Dataflow Programming using Actor Machines for High-Level Synthesis. FPGA Endri Bezati, Mahyar Emami, James R. Larus
2020	J	`jnl`	Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs. J. Signal Process. Syst. Anatoly Prihozhy, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
2020	—	`conf`	Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis. SiPS Aurelien Bloch, Endri Bezati, Marco Mattavelli
2019	Misc	`conf`	An Heterogeneous Compiler of Dataflow Programs for Zynq Platforms. ICASSP Endri Bezati, Simone Casale Brunet, Romuald Mosqueron, Marco Mattavelli
2019	—	`conf`	Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism. ICCS (5) Aurelien Bloch, Endri Bezati, Marco Mattavelli
2019	C	`conf`	Dataflow-based Heterogeneous Code Generator for IoT Applications. MODELSWARD Gábor Paller, Endri Bezati, Nebojsa Tausan, Gabor Farkas, Gábor Élö
2018	—	`conf`	Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines. SiPS Anatoly Prihozhy, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
2018	J	`jnl`	High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs. IEEE Trans. Multi Scale Comput. Syst. Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
2018	—	`conf`	Shared-variable Synchronization Approaches for Dynamic Data Flow Programs. SiPS Apostolos Modas, Simone Casale Brunet, Robert J. Stewart, Endri Bezati, Junaid Jameel Ahmad, Marco Mattavelli
2018	B	`conf`	Towards in the Field Fast Pathogens Detection Using FPGAs. FPL Simone Casale Brunet, Thierry Schüpbach, Nicolas Guex, Christian Iseli, Alan J. Bridge, Dmitry Kuznetsov, Christian J. A. Sigrist, Phillippe Lemercier, Ioannis Xenarios, Endri Bezati
2017	—	`conf`	Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms. EUSIPCO Malgorzata Michalska, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
2017	J	`jnl`	Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
2017	—	`conf`	Design space exploration of dataflow-based Smith-Waterman FPGA implementations. SiPS Simone Casale Brunet, Endri Bezati, Marco Mattavelli
2017	Misc	`conf`	Execution trace graph based interface synthesis of signal processing dataflow programs for heterogeneous MPSoCs. ACSSC Endri Bezati, Simone Casale Brunet, Marco Mattavelli
2017	Misc	`conf`	High level synthesis of Smith-Waterman dataflow implementations. ICASSP Simone Casale Brunet, Endri Bezati, Marco Mattavelli
2017	Misc	`conf`	Profiling of dynamic dataflow programs on MPSoC multi-core architectures. ACSSC Simone Casale Brunet, Endri Bezati, Aurelien Bloch, Marco Mattavelli
2016	Misc	`conf`	A Partition Scheduler Model for Dynamic Dataflow Programs. ICCS Malgorzata Michalska, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
2016	J	`jnl`	Automated Design Flow for Multi-Functional Dataflow-Based Platforms. J. Signal Process. Syst. Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
2016	J	`jnl`	Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques - Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies. J. Signal Process. Syst. Massimo Canale, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck
2016	—	`conf`	Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures. MCSoC Malgorzata Michalska, Nicolas Zufferey, Endri Bezati, Marco Mattavelli
2016	—	`conf`	High-Precision Performance Estimation of Dynamic Dataflow Programs. MCSoC Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
2016	—	`conf`	High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms. SAMOS Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
2016	Misc	`conf`	High-level system synthesis and optimization of dataflow programs for MPSoCs. ACSSC Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
2016	—	`conf`	Performance estimation of program partitions on multi-core platforms. PATMOS Malgorzata Michalska, J. J. Ahmad, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
2016	—	`conf`	Programming Models and Methods for Heterogeneous Parallel Embedded Systems. MCSoC Simone Casale Brunet, Endri Bezati, Marco Mattavelli
2016	Misc	`conf`	Trace-based manycore partitioning of stream-processing applications. ACSSC Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck
2015	Misc	`conf`	Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs. ICCS Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
2015	—	`—`	High-level synthesis of dataflow programs for heterogeneous platforms: design flow tools and design space exploration. Endri Bezati
2015	J	`jnl`	Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anatoly Prihozhy, Endri Bezati, Ab Al-Hadi Ab Rahman, Marco Mattavelli
2014	—	`conf`	Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case. ICSAMOS Carlo Sau, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
2014	Misc	`conf`	Dataflow machines. ACSSC Jörn W. Janneck, Gustav Cedersjö, Endri Bezati, Simone Casale Brunet
2014	—	`conf`	Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. SiPS Massimo Canale, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck
2014	—	`conf`	Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. DASIP Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Massimo Canale, Jörn W. Janneck
2014	J	`jnl`	High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms. J. Real Time Image Process. Endri Bezati, Richard Thavot, Ghislain Roquier, Marco Mattavelli
2014	—	`conf`	TURNUS: An open-source design space exploration framework for dynamic stream programs. DASIP Simone Casale Brunet, M. Wiszniewska, Endri Bezati, Marco Mattavelli, Jörn W. Janneck, Massimo Canale
2013	—	`conf`	Design space exploration and implementation of RVC-CAL applications using the TURNUS framework. DASIP Simone Casale Brunet, Endri Bezati, Claudio Alberti, Ghislain Roquier, Marco Mattavelli, Jörn W. Janneck, Jani Boutellier
2013	C	`conf`	High-level synthesis of dataflow programs for signal processing systems. ISPA Endri Bezati, Marco Mattavelli, Jörn W. Janneck
2013	C	`conf`	Live demonstration: High level software and hardware synthesis of dataflow programs. ISCAS Endri Bezati, Ghislain Roquier, Marco Mattavelli
2013	J	`jnl`	Methods to explore design space for MPEG RMC codec specifications. Signal Process. Image Commun. Simone Casale Brunet, Abdallah Elguindy, Endri Bezati, Richard Thavot, Ghislain Roquier, Marco Mattavelli, Jörn W. Janneck
2013	Misc	`conf`	Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications. ACSSC Simone Casale Brunet, Endri Bezati, Claudio Alberti, Marco Mattavelli, Edoardo Amaldi, Jörn W. Janneck
2013	—	`conf`	Partitioning and optimization of high level stream applications for multi clock domain architectures. SiPS Simone Casale Brunet, Endri Bezati, Claudio Alberti, Marco Mattavelli, Edoardo Amaldi, Jörn W. Janneck
2012	—	`conf`	Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program. DASIP Ab Al-Hadi Ab Rahman, Richard Thavot, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
2012	J	`jnl`	Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs. J. Electr. Comput. Eng. Ghislain Roquier, Endri Bezati, Marco Mattavelli
2011	—	`conf`	A unified hardware/software co-synthesis solution for signal processing systems. DASIP Endri Bezati, Hervé Yviquel, Mickaël Raulet, Marco Mattavelli
2011	—	`conf`	Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms. DASIP Ghislain Roquier, Endri Bezati, Richard Thavot, Marco Mattavelli
2010	—	`conf`	RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding. DASIP Endri Bezati, Marco Mattavelli, Mickaël Raulet