Emmanuel Casseau

86 papers A 2B 1C 10Misc 4Journal 27Unranked 42

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	DyEKF: Dynamic Protection of Approximate NoC Communications Against Hardware Trojan Attacks. SOCC Hamza Amara, Cédric Killian, Daniel Chillet, Emmanuel Casseau
2025	J	`jnl`	Intelligent4DSE: Optimizing High-Level Synthesis Design Space Exploration with Graph Neural Networks and Large Language Models. CoRR Lei Xu, Shanshan Wang, Emmanuel Casseau, Chenglong Xiao
2024	J	`jnl`	Algorithms with improved delay for enumerating connected induced subgraphs of a large cardinality. Inf. Process. Lett. Shanshan Wang, Chenglong Xiao, Emmanuel Casseau
2024	—	`conf`	Importance Resides in Activations: Fast Input-Based Nonlinearity Pruning. ICONIP (9) Baptiste Rossigneux, Vincent Lorrain, Inna Kucher, Emmanuel Casseau
2024	—	`conf`	Mitigation of Hardware Trojan in NoC using Delta-Based Compression. SOCC Hamza Amara, Cédric Killian, Daniel Chillet, Emmanuel Casseau
2023	J	`jnl`	Near-optimal energy-efficient partial-duplication task mapping of real-time parallel applications. J. Syst. Archit. Minyu Cui, Angeliki Kritikakou, Lei Mo, Emmanuel Casseau
2023	J	`jnl`	Online fault tolerant energy-aware algorithm for CubeSats. Sustain. Comput. Informatics Syst. Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
2023	—	`conf`	Surround the Nonlinearity: Inserting Foldable Convolutional Autoencoders to Reduce Activation Footprint. ICCV (Workshops) Baptiste Rossigneux, Inna Kucher, Vincent Lorrain, Emmanuel Casseau
2022	C	`conf`	Cache management in MASCARA-FPGA: from coalescing heuristic to replacement policy. DaMoN Van Long Nguyen Huu, Laurent d'Orazio, Emmanuel Casseau, Julien Lallet
2022	J	`jnl`	Energy-Efficient Partial-Duplication Task Mapping Under Multiple DVFS Schemes. Int. J. Parallel Program. Minyu Cui, Angeliki Kritikakou, Lei Mo, Emmanuel Casseau
2021	J	`jnl`	An Optimal Algorithm for Enumerating Connected Convex Subgraphs in Acyclic Digraphs. IEEE Trans. Circuits Syst. II Express Briefs Chenglong Xiao, Shanshan Wang, Wanjun Liu, Xinlin Wang, Emmanuel Casseau
2021	J	`jnl`	An algorithm with improved delay for enumerating connected induced subgraphs of a large cardinality. CoRR Shanshan Wang, Chenglong Xiao, Emmanuel Casseau
2021	A	`conf`	Fault-Tolerant Mapping of Real-Time Parallel Applications under multiple DVFS schemes. RTAS Minyu Cui, Angeliki Kritikakou, Lei Mo, Emmanuel Casseau
2021	J	`jnl`	Improving the CubeSat reliability thanks to a multiprocessor system using fault tolerant online scheduling. Microprocess. Microsystems Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
2021	B	`conf`	MASCARA-FPGA cooperation model: Query Trimming through accelerators. SSDBM Van Long Nguyen Huu, Laurent d'Orazio, Emmanuel Casseau, Julien Lallet
2021	Misc	`conf`	Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum. VTS Emmanuel Casseau, Petr Dobiás, Oliver Sinnen, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Alessandro Savino, Stefano Di Carlo, Maurizio Rebaudengo, Alberto Bosio
2020	—	`conf`	Energy-Aware Partial-Duplication Task Mapping Under Real-Time and Reliability Constraints. SAMOS Minyu Cui, Lei Mo, Angeliki Kritikakou, Emmanuel Casseau
2020	C	`conf`	Evaluation of Fault Tolerant Online Scheduling Algorithms for CubeSats. DSD Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
2020	—	`conf`	Fault-Tolerant Online Scheduling Algorithms for CubeSats. PARMA-DITAM@HiPEAC Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
2020	J	`jnl`	MASCARA (ModulAr Semantic CAching fRAmework) towards FPGA Acceleration for IoT Security Monitoring. Open J. Internet Things Van Long Nguyen Huu, Julien Lallet, Emmanuel Casseau, Laurent d'Orazio
2019	—	`conf`	Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors. DASIP Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys, Emmanuel Casseau
2018	—	`conf`	Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems. DASIP Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
2018	C	`conf`	Restricted Scheduling Windows for Dynamic Fault-Tolerant Primary/Backup Approach-Based Scheduling on Embedded Systems. SCOPES Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
2017	—	`conf`	An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy. DASIP Imran Wali, Emmanuel Casseau, Arnaud Tisserand
2017	J	`jnl`	Parallel custom instruction identification for extensible processors. J. Syst. Archit. Chenglong Xiao, Shanshan Wang, Wanjun Liu, Emmanuel Casseau
2016	J	`jnl`	A comparison of heuristic algorithms for custom instruction selection. Microprocess. Microsystems Shanshan Wang, Chenglong Xiao, Wanjun Liu, Emmanuel Casseau
2016	—	`conf`	Demo abstract: FPGA-based implementation of a flexible FFT dedicated to LTE standard. DASIP Mai-Thanh Tran, Emmanuel Casseau, Matthieu Gautier
2016	—	`conf`	On the FPGA-Based Implementation of a Flexible Waveform from a High-Level Description: Application to LTE FFT Case Study. CrownCom Mai-Thanh Tran, Matthieu Gautier, Emmanuel Casseau
2015	—	`conf`	Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms. DASIP Kevin J. M. Martin, Yvan Eustache, Jean-Philippe Diguet, Thanh Dinh Ngo, Emmanuel Casseau, Yaset Oliva
2015	J	`jnl`	Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs. J. Signal Process. Syst. Hervé Yviquel, Alexandre Sanchez, Pekka Jääskeläinen, Jarmo Takala, Mickaël Raulet, Emmanuel Casseau
2015	—	`conf`	Selecting most profitable instruction-set extensions using ant colony heuristic. DASIP Shanshan Wang, Chenglong Xiao, Wanjun Liu, Emmanuel Casseau, Xiao Yang
2015	—	`conf`	Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m). ISVLSI Jérémy Métairie, Arnaud Tisserand, Emmanuel Casseau
2014	J	`jnl`	Automatic custom instruction identification for application-specific instruction set processors. Microprocess. Microsystems Chenglong Xiao, Emmanuel Casseau, Shanshan Wang, Wanjun Liu
2014	Misc	`conf`	Efficient software synthesis of dynamic dataflow programs. ICASSP Hervé Yviquel, Alexandre Sanchez, Pekka Jääskeläinen, Jarmo Takala, Mickaël Raulet, Emmanuel Casseau
2014	C	`conf`	Improving high-level synthesis effectiveness through custom operator identification. ISCAS Chenglong Xiao, Emmanuel Casseau
2014	—	`conf`	Orcc's compa-backend demonstration. DASIP Yaset Oliva, Emmanuel Casseau, Kevin J. M. Martin, Pierre Bomel, Jean-Philippe Diguet, Hervé Yviquel, Mickaël Raulet, Erwan Raffin, Laurent Morin
2014	—	`conf`	Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architecture. ReConFig Quang-Hoa Le, Emmanuel Casseau, Antoine Courtay
2013	J	`jnl`	Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs. Signal Process. Image Commun. Hervé Yviquel, Jani Boutellier, Mickaël Raulet, Emmanuel Casseau
2013	C	`conf`	Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms. ISPA Hervé Yviquel, Emmanuel Casseau, Mickaël Raulet, Pekka Jääskeläinen, Jarmo Takala
2012	J	`jnl`	Design of multi-mode application-specific cores based on high-level synthesis. Integr. Emmanuel Casseau, Bertrand Le Gal
2012	J	`jnl`	Exact custom instruction enumeration for extensible processors. Integr. Chenglong Xiao, Emmanuel Casseau
2012	J	`jnl`	Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture. Int. J. Embed. Real Time Commun. Syst. Erwan Raffin, Christophe Wolinski, François Charot, Emmanuel Casseau, Antoine Floch, Krzysztof Kuchcinski, Stéphane Chevobbe, Stéphane Guyetant
2011	—	`conf`	An efficient algorithm for custom instruction enumeration. ACM Great Lakes Symposium on VLSI Chenglong Xiao, Emmanuel Casseau
2011	—	`conf`	Efficient custom instruction enumeration for extensible processors. ASAP Chenglong Xiao, Emmanuel Casseau
2011	—	`conf`	Efficient maximal convex custom instruction enumeration for extensible processors. DASIP Chenglong Xiao, Emmanuel Casseau
2011	—	`conf`	Efficient multicore scheduling of dataflow process networks. SiPS Hervé Yviquel, Emmanuel Casseau, Matthieu Wipliez, Mickaël Raulet
2011	Misc	`conf`	Exploiting reconfigurable SWP operators for multimedia applications. ICASSP Daniel Ménard, Hai-Nam Nguyen, François Charot, Stéphane Guyetant, Jérémie Guillot, Erwan Raffin, Emmanuel Casseau
2011	J	`jnl`	Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design. EURASIP J. Adv. Signal Process. Bertrand Le Gal, Emmanuel Casseau
2011	—	`conf`	Stochastic modeling for floating-point to fixed-point conversion. SiPS Andrei Banciu, Emmanuel Casseau, Daniel Ménard, Thierry Michel
2011	J	`jnl`	Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis. J. Signal Process. Syst. Bertrand Le Gal, Emmanuel Casseau
2010	—	`conf`	A case study of the stochastic modeling approach for range estimation. DASIP Andrei Banciu, Emmanuel Casseau, Daniel Ménard, Thierry Michel
2010	—	`conf`	A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design. DASIP Cecile Beaumin, Olivier Sentieys, Emmanuel Casseau, Arnaud Carer
2010	J	`jnl`	High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet
2010	—	`conf`	Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture. DASIP Erwan Raffin, Christophe Wolinski, François Charot, Krzysztof Kuchcinski, Stéphane Guyetant, Stéphane Chevobbe, Emmanuel Casseau
2009	—	`conf`	Automated multimode system design for high performance DSP applications. EUSIPCO Bertrand Le Gal, Emmanuel Casseau
2009	—	`conf`	High-level synthesis for the design of FPGA-based signal processing systems. ICSAMOS Emmanuel Casseau, Bertrand Le Gal
2009	—	`conf`	Reconfigurable Operator Based Multimedia Embedded Processor. ARC Daniel Ménard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David
2009	—	`conf`	Reconfigurable SWP Operator for Multimedia Processing. ASAP Shafqat Khan, Emmanuel Casseau, Daniel Ménard
2008	J	`jnl`	Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet
2008	J	`jnl`	Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau. Tech. Sci. Informatiques Bertrand Le Gal, Emmanuel Casseau, Caaliph Andriamisaina
2007	A	`conf`	A design flow dedicated to multi-mode architectures for DSP applications. ICCAD Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
2007	J	`jnl`	Constrained algorithmic IP design for system-on-chip. Integr. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
2007	C	`conf`	Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications. FDL Sylvain Huet, Sébastien Le Nours, Olivier Pasquier, Emmanuel Casseau
2007	—	`conf`	HLS design flow for the synthesis of multimode systems under multiple constraints. ICECS Bertrand Le Gal, Lilian Bossuet, Shafqat Khan, Emmanuel Casseau
2007	—	`conf`	Synthesis of Multimode digital signal processing systems. AHS Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy
2006	C	`conf`	A Computation Core for Communication Refinement of Digital Signal Processing Algorithms. DSD Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
2006	J	`jnl`	A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
2006	—	`conf`	Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems. SoCC Bertrand Le Gal, Caaliph Andriamisaina, Emmanuel Casseau
2006	—	`conf`	Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. SiPS Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau
2006	J	`jnl`	Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. Signal Process. Guillaume Savaton, Emmanuel Casseau, Eric Martin
2006	J	`jnl`	G729 Voice Decoder Design. J. VLSI Signal Process. Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin
2006	C	`conf`	Hardware Communication Refinement in Digital Signal Processing. FDL Sylvain Huet, Emmanuel Casseau, Olivier Pasquier, Sébastien Le Nours
2006	—	`conf`	IP Generation Targeting Multiple Bit-Width Standards. ICECS Bertrand Le Gal, Emmanuel Casseau
2005	—	`conf`	C-based rapid prototyping for digital signal processing. EUSIPCO Emmanuel Casseau, Bertrand Le Gal, Pierre Bomel, Christophe Jégo, Sylvain Huet, Eric Martin
2005	C	`conf`	Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design. IEEE International Workshop on Rapid System Prototyping Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
2005	C	`conf`	Hardware Virtual Components Compliant with Communication System Standards. DSD Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno
2005	—	`conf`	Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. ISVLSI Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin
2005	—	`conf`	Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses. EUSIPCO Bertrand Le Gal, Emmanuel Casseau, Eric Martin
2004	—	`conf`	Reed-Solomon behavioral virtual component for communication systems. ISCAS (4) Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin
2004	J	`jnl`	Synthèse architecturale d'applications temps réel pour technologies submicroniques. Tech. Sci. Informatiques Emmanuel Casseau, Christophe Jégo, Eric Martin
2002	—	`conf`	SoC design using behavioral level virtual components. ICECS Emmanuel Casseau
2001	—	`conf`	Architectural synthesis of digital signal processing applications dedicated to submicron technologies. ICECS Emmanuel Casseau, Christophe Jégo, Eric Martin
1999	—	`conf`	Architectural Synthesis with Interconnection Cost Control. VLSI Christophe Jégo, Emmanuel Casseau, Eric Martin
1996	—	`conf`	Architecture of a high-rate VLSI Viterbi decoder. ICECS Emmanuel Casseau, Eric Lüthi
1996	—	`conf`	High Rate Soft Output Viterbi Decoder. ED&TC Eric Lüthi, Emmanuel Casseau
1994	Misc	`conf`	A Linear Systolic Array for LU Decomposition. VLSI Design Emmanuel Casseau, Dominique Degrugillier