Elizabeth M. Rudnick

64 papers A* 5A 15B 2C 1Misc 13Journal 17Unranked 10
YearRankTypeTitle / Venue / Authors
2004 J jnl
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing.
IEEE Trans. Computers
Dirk Niggemeyer, Elizabeth M. Rudnick
2003 J jnl
A data acquisition methodology for on-chip repair of embedded memories.
ACM Trans. Design Autom. Electr. Syst.
Dirk Niggemeyer, Elizabeth M. Rudnick
2002 B conf
A Genetic Testing Framework for Digital Integrated Circuits.
ICTAI
Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick
2002 A conf
Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm.
GECCO
Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick
2002 A* conf
Low-cost sequential ATPG with clock-control DFT.
DAC
Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick
2001 B conf
A genetic approach to automatic bias generation for biased random instruction generation.
CEC
Mrinal Bose, Jongshin Shin, Elizabeth M. Rudnick, Todd Dukes, Magdy Abadir
2001 A conf
At-speed logic BIST using a frozen clock testing strategy.
ITC
Jongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici
2001 — conf
Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.
IOLTW
Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir
2001 Misc conf
Automatic Generation of Diagnostic March Tests.
VTS
Dirk Niggemeyer, Elizabeth M. Rudnick
2001 J jnl
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists.
ACM Trans. Design Autom. Electr. Syst.
Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty
2001 — conf
Sequential ATPG Using Combinational Algorithms.
LATW
Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick
2001 J jnl
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach.
J. Electron. Test.
Franco Fummi, Marco Boschini, Xiaoming Yu, Elizabeth M. Rudnick
2001 J jnl
Use of a field programmable gate array for education in manufacturing test and automatic test equipment.
IEEE Trans. Educ.
Dirk Niggemeyer, Kevin J. Stephano, Elizabeth M. Rudnick
2000 J jnl
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.
J. Electron. Test.
Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick
2000 J jnl
Bridge fault diagnosis using stuck-at fault simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jue Wu, Elizabeth M. Rudnick
2000 — conf
Combining symbolic and genetic techniques for efficient sequential circuit test generation.
ETW
Marco Boschini, Xiaoming Yu, Franco Fummi, Elizabeth M. Rudnick
2000 J jnl
Compact Test Generation Using a Frozen Clock Testing Strategy.
J. Inf. Sci. Eng.
Elizabeth M. Rudnick, Miron Abramovici
2000 — conf
Diagnostic Testing of Embedded Memories Based on Output Tracing.
MTDT
Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Redeker
2000 A conf
Diagnostic Testing of Embedded Memories Using BIST.
DATE
Timothy J. Bergfeld, Dirk Niggemeyer, Elizabeth M. Rudnick
2000 A conf
Diagnostic test generation for sequential circuits.
ITC
Xiaoming Yu, Jue Wu, Elizabeth M. Rudnick
2000 J jnl
Dynamic state traversal for sequential circuit test generation.
ACM Trans. Design Autom. Electr. Syst.
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
2000 J jnl
Peak power estimation of VLSI circuits: new peak power measures.
IEEE Trans. Very Large Scale Integr. Syst.
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1999 Misc conf
A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults.
VLSI Design
Jue Wu, Elizabeth M. Rudnick
1999 A conf
A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis.
DATE
Jue Wu, Gary S. Greenstein, Elizabeth M. Rudnick
1999 J jnl
Efficient Techniques for Dynamic Test Sequence Compaction.
IEEE Trans. Computers
Elizabeth M. Rudnick, Janak H. Patel
1999 J jnl
Fast Static Compaction Algorithms for Sequential Circuit Test Vectors.
IEEE Trans. Computers
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1999 A conf
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy.
DATE
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici
1999 — ch.
Microprocessor Design Verification.
The VLSI Handbook
Vikram Iyengar, Elizabeth M. Rudnick
1998 J jnl
Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1998 C conf
Enhancing topological ATPG with high-level information and symbolic techniques.
ICCD
Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda, Roberto Vietti
1998 A conf
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques.
DATE
Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1998 Misc conf
Partial Scan Selection Based on Dynamic Reachability and Observability Information.
VLSI Design
Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel
1997 J jnl
A genetic algorithm framework for test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
1997 — conf
Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation.
Workshop on Parallel and Distributed Simulation
Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel
1997 Misc conf
Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits.
VLSI Design
Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel
1997 A conf
Effects of delay models on peak power estimation of VLSI sequential circuits.
ICCAD
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1997 Misc conf
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors.
VTS
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1997 A conf
K2: an estimator for peak sustainable power of VLSI circuits.
ISLPED
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1997 Misc conf
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation.
VLSI Design
Elizabeth M. Rudnick, Janak H. Patel
1997 Misc conf
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation.
VLSI Design
Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee
1997 A conf
Putting the Squeeze on Test Sequences.
ITC
Elizabeth M. Rudnick, Janak H. Patel
1997 Misc conf
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation.
VTS
Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee
1997 — conf
Sequential circuit test generation using dynamic state traversal.
ED&TC
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1997 Misc conf
Static logic implication with application to redundancy identification.
VTS
Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel
1996 J jnl
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults.
IEEE Trans. Computers
Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi
1996 — conf
Alternating Strategies for Sequential Circuit ATPG.
ED&TC
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1996 Misc conf
Automatic test generation using genetically-engineered distinguishing sequences.
VTS
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1996 A conf
Enhancing high-level control-flow for improved testability.
ICCAD
Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel
1996 Misc conf
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.
VTS
Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel
1996 A conf
On Potential Fault Detection in Sequential Circuits.
ITC
Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz
1996 A conf
Simulation-based techniques for dynamic test sequence compaction.
ICCAD
Elizabeth M. Rudnick, Janak H. Patel
1996 — conf
Testability Insertion in Behavioral Descriptions.
ISSS
Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel
1995 Misc conf
A genetic approach to test application time reduction for full scan and partial scan circuits.
VLSI Design
Elizabeth M. Rudnick, Janak H. Patel
1995 A* conf
Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation.
DAC
Elizabeth M. Rudnick, Janak H. Patel
1995 A* conf
Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists.
DAC
Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel
1995 J jnl
Sequential circuit testability enhancement using a nonscan approach.
IEEE Trans. Very Large Scale Integr. Syst.
Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel
1994 J jnl
An observability enhancement approach for improved testability and at-speed test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel
1994 — conf
Application of Simple Genetic Algorithms to Sequential Circuit Test Generation.
EDAC-ETC-EUROASIC
Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel
1994 A* conf
Sequential Circuit Test Generation in a Genetic Algorithm Framework.
DAC
Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
1993 — conf
A Fast and Accurate Gate-Level Transient Fault Simulation Environment.
FTCS
Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer
1993 A* conf
Non-Scan Design-for-Testability Techniques for Sequential Circuits.
DAC
Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel
1992 A conf
Diagnostic Fault Simulation of Sequential Circuits.
ITC
Elizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel
1992 Misc conf
Probe point insertion for at-speed test.
VTS
Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel
1991 A conf
Methods for Reducing Events in Sequential Circuit Fault Simulation.
ICCAD
Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel