Elizabeth J. Brauer

19 papers B 1C 6Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2009 J jnl
Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP.
Microelectron. J.
Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici
2008 — conf
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits.
PATMOS
Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici
2008 C conf
Improving the power-delay product in SCL circuits using source follower output stage.
ISCAS
Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer
2008 J jnl
Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications.
IEEE J. Solid State Circuits
Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric A. Vittoz
2007 — conf
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept.
ESSCIRC
Armin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer
2006 C conf
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.
VLSI-SoC
Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer
2006 C conf
Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design.
ISCAS
Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici
2004 — conf
Finding efficient inductor geometries in digital CMOS process for RF applications.
Circuits, Signals, and Systems
Elizabeth J. Brauer, Vikram Magoon
2004 — conf
Low noise MCML prefix adders using 0.18 µm CMOS technology.
Circuits, Signals, and Systems
Elizabeth J. Brauer, Yusuf Leblebici
2004 — conf
Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic.
Circuits, Signals, and Systems
Elizabeth J. Brauer, Yusuf Leblebici
1999 B conf
Hardware implementation of a neural network pattern shaper algorithm.
IJCNN
Elizabeth J. Brauer, James J. Abbas, Brian Callaway, Joshua Colvin, John Farris
1998 J jnl
Additive Decomposition Applied to the Semiconductor Drift-Diffusion Model.
VLSI Design
Elizabeth J. Brauer, Marek Turowski, James M. McDonough
1997 — conf
A Full-Swing Bootstrapped BiCMOS Buffer.
Great Lakes Symposium on VLSI
Elizabeth J. Brauer, Pradeep Elamanchili
1997 — conf
Analog Circuit Model of Lamprey Unit Pattern Generator.
Great Lakes Symposium on VLSI
Elizabeth J. Brauer, Ranu Jung, Denise M. Wilson, James J. Abbas
1997 — conf
Sensitivity analysis of an analog circuit model of lamprey unit pattern generator.
ICNN
Elizabeth J. Brauer, Ranu Jung, Denise M. Wilson, James J. Abbas
1995 C conf
An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations.
ISCAS
Elizabeth J. Brauer, Sung-Mo Kang
1995 J jnl
An algorithm for functional verification of digital ECL circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elizabeth J. Brauer, Sung-Mo Kang
1995 C conf
Estimating Node Voltages in Bipolar Circuits Using Linear Programming.
ISCAS
Elizabeth J. Brauer, Sung-Mo Kang
1993 C conf
Functional Verification of ECL Circuits Including Voltage Regulators.
ISCAS
Elizabeth J. Brauer, Sung-Mo Kang