Elisardo Antelo

47 papers C 14Journal 26Unranked 7

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	ENBB Processor: Towards the ExaScale Numerical Brain Box [Position Paper]. CoRR Elisardo Antelo
2019	C	`conf`	New 3D Projection Transformation for Point Clouds. ARITH Álvaro Vázquez, Elisardo Antelo
2017	C	`conf`	A Number System Approach for Adder Topologies. ARITH Álvaro Vázquez, Elisardo Antelo
2017	C	`conf`	A Sum Error Detection Scheme for Decimal Arithmetic. ARITH Álvaro Vázquez, Elisardo Antelo
2017	J	`jnl`	Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. Elisardo Antelo, Paolo Montuschi, Alberto Nannarelli
2016	J	`jnl`	Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors. Comput. J. Lois Orosa, Javier D. Bruguera, Elisardo Antelo
2014	J	`jnl`	Fast Radix-10 Multiplication Using Redundant BCD Codes. IEEE Trans. Computers Álvaro Vázquez, Elisardo Antelo, Javier D. Bruguera
2012	J	`jnl`	FlexSig: Implementing flexible hardware signatures. ACM Trans. Archit. Code Optim. Lois Orosa, Elisardo Antelo, Javier D. Bruguera
2012	J	`jnl`	Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers Elisardo Antelo, David Hough, Paolo Ienne
2012	J	`jnl`	Redundant Floating-Point Decimal CORDIC Algorithm. IEEE Trans. Computers Álvaro Vázquez, Julio Villalba-Moreno, Elisardo Antelo, Emilio L. Zapata
2011	C	`ed.`	20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011 IEEE Symposium on Computer Arithmetic Elisardo Antelo, David Hough, Paolo Ienne
2011	J	`jnl`	Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers. IEEE Trans. Computers Fabrizio Lamberti, Nikolaos Andrikos, Elisardo Antelo, Paolo Montuschi
2010	J	`jnl`	Improved Design of High-Performance Parallel Decimal Multipliers. IEEE Trans. Computers Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi
2009	J	`jnl`	A Comment on "Beyond Fat-tree: Unidirectional Load-Balanced Multistage Interconnection Network". IEEE Comput. Archit. Lett. Elisardo Antelo
2009	C	`conf`	A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding. IEEE Symposium on Computer Arithmetic Álvaro Vázquez, Elisardo Antelo
2009	C	`conf`	Computation of Decimal Transcendental Functions Using the CORDIC Algorithm. IEEE Symposium on Computer Arithmetic Álvaro Vázquez, Julio Villalba, Elisardo Antelo
2008	J	`jnl`	A Low-Latency Pipelined 2D and 3D CORDIC Processors. IEEE Trans. Computers Elisardo Antelo, Julio Villalba, Emilio L. Zapata
2008	—	`conf`	New insights on Ling adders. ASAP Álvaro Vázquez, Elisardo Antelo
2007	C	`conf`	A New Family of High.Performance Parallel Decimal Multipliers. IEEE Symposium on Computer Arithmetic Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi
2007	C	`conf`	A radix-10 SRT divider based on alternative BCD codings. ICCD Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi
2005	J	`jnl`	Digit-Recurrence Dividers with Reduced Logical Depth. IEEE Trans. Computers Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
2005	J	`jnl`	High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics. IEEE Trans. Computers Tomás Lang, Elisardo Antelo
2005	C	`conf`	Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. IEEE Symposium on Computer Arithmetic Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
2005	C	`conf`	Low Latency Pipelined Circular CORDIC. IEEE Symposium on Computer Arithmetic Elisardo Antelo, Julio Villalba
2003	J	`jnl`	Implementation of the Exponential Function in a Floating-Point Unit. J. VLSI Signal Process. Álvaro Vázquez, Elisardo Antelo
2003	J	`jnl`	Radix-4 Reciprocal Square-Root and Its Combination with Division and Square Root. IEEE Trans. Computers Tomás Lang, Elisardo Antelo
2002	—	`conf`	Fast Radix-4 Retimed Division with Selection by Comparisons. ASAP Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
2001	C	`conf`	Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation. IEEE Symposium on Computer Arithmetic Tomás Lang, Elisardo Antelo
2000	J	`jnl`	CORDIC-Based Computation of ArcCos. J. VLSI Signal Process. Tomás Lang, Elisardo Antelo
2000	J	`jnl`	Very-High Radix CORDIC Rotation Based on Selection by Rounding. J. VLSI Signal Process. Elisardo Antelo, Tomás Lang, Javier D. Bruguera
2000	J	`jnl`	Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. IEEE Trans. Computers Elisardo Antelo, Tomás Lang, Javier D. Bruguera
1999	C	`conf`	Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. IEEE Symposium on Computer Arithmetic Elisardo Antelo, Tomás Lang, Javier D. Bruguera
1998	J	`jnl`	A novel design of a two operand normalization circuit. IEEE Trans. Very Large Scale Integr. Syst. Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata
1998	J	`jnl`	CORDIC Vectoring with Arbitrary Target Value. IEEE Trans. Computers Tomás Lang, Elisardo Antelo
1998	J	`jnl`	Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. IEEE Trans. Computers Elisardo Antelo, Tomás Lang, Javier D. Bruguera
1998	J	`jnl`	Radix-4 Vectoring CORDIC Algorithm and Architectures. J. VLSI Signal Process. Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
1997	C	`conf`	CORDIC Vectoring with Arbitrary Target Value. IEEE Symposium on Computer Arithmetic Tomás Lang, Elisardo Antelo
1997	—	`conf`	CORDIC-based computation of arccos and arcsin. ASAP Tomás Lang, Elisardo Antelo
1997	J	`jnl`	Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. IEEE Trans. Computers Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Emilio L. Zapata
1997	J	`jnl`	High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata
1996	—	`conf`	High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata
1996	—	`conf`	Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
1996	J	`jnl`	Unified Mixed Radix 2-4 Redundant CORDIC Processor. IEEE Trans. Computers Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata
1995	—	`conf`	CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP Julio Villalba, José Antonio Hidalgo López, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
1995	—	`conf`	Digit On-line Large Radix CORDIC Rotator. ASAP Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
1995	C	`conf`	Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
1993	J	`jnl`	Design of a Pipelined Radix 4 CORDIC Processor. Parallel Comput. Javier D. Bruguera, Elisardo Antelo, Emilio L. Zapata