Elio Consoli

28 papers C 5Journal 11Unranked 12
YearRankTypeTitle / Venue / Authors
2025 — conf
Detailed Modeling of a PFM Buck-Boost Converter suitable for Low Power Applications.
PRIME
Carla Caruso, Elio Consoli, Gaetano Palumbo, Giuseppe Patti
2015 — conf
Comparative analysis of the robustness of master-slave flip-flops against variations.
ICECS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2015 — conf
PVT variations in differential flip-flops: A comparative analysis.
ECCTD
Massimo Alioto, Gaetano Palumbo, Elio Consoli
2015 — conf
Variability budgetin pulsed flip-flops.
NEWCAS
Massimo Alioto, Gaetano Palumbo, Elio Consoli
2015 J jnl
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2015 J jnl
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2014 J jnl
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches.
IEEE Trans. Very Large Scale Integr. Syst.
Elio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto
2013 J jnl
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions.
IEEE J. Solid State Circuits
Massimo Alioto, Elio Consoli, Jan M. Rabaey
2012 J jnl
An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
2012 — conf
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS.
ISSCC
Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey
2012 — conf
EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS.
CICC
Massimo Alioto, Elio Consoli, Jan M. Rabaey
2012 J jnl
From energy-delay metrics to constraints on the design of digital circuits.
Int. J. Circuit Theory Appl.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2012 C conf
Logic gates dynamic modeling by means of an ultra-compact MOS model.
ISCAS
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
2012 J jnl
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst.
Elio Consoli, Gaetano Palumbo, Melita Pennisi
2011 — conf
An ultra-compact MOS model in nanometer technologies.
ECCTD
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
2011 J jnl
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2011 J jnl
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2011 C conf
DET FF topologies: A detailed investigation in the energy-delay-area domain.
ISCAS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2011 — conf
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model.
ECCTD
Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo
2011 C conf
TG Master-Slave FFs: High-speed optimization.
ISCAS
Elio Consoli, Gaetano Palumbo, Melita Pennisi
2010 C conf
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.
ISCAS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 J jnl
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 J jnl
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 — conf
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits.
PATMOS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2009 — conf
Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits.
ECCTD
Massimo Alioto, Elio Consoli, Gaetano Palumbo, Melita Pennisi
2009 — conf
Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design.
ECCTD
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2009 C conf
Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits.
ISCAS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2009 — conf
Optimum clock slope for flip-flops within a clock domain: Analysis and a case study.
ICECS
Massimo Alioto, Elio Consoli, Gaetano Palumbo