Elias Vansteenkiste

22 papers A 1B 6Misc 1Journal 5Unranked 9

Year	Rank	Type	Title / Venue / Authors
2019	Misc	`conf`	CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router. FCCM Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
2018	B	`conf`	Hierarchical Force-Based Block Spreading for Analytical FPGA Placement. FPL Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
2018	J	`jnl`	How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
2017	—	`conf`	Liquid: High quality scalable placement for large heterogeneous FPGAs. FPT Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
2017	J	`jnl`	Taming Adversarial Domain Transfer with Structural Constraints for Image Enhancement. CoRR Elias Vansteenkiste, Patrick Kern
2016	—	`conf`	A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications. IPDPS Workshops Amit Kulkarni, Elias Vansteenkiste, Dirk Stroobandt, Andreas Brokalakis, Antonis Nikitakis
2016	—	`conf`	EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures. ReCoSoC Dirk Stroobandt, Ana Lucia Varbanescu, Catalin Bogdan Ciobanu, Muhammed Al Kadi, Andreas Brokalakis, George Charitopoulos, Tim Todman, Xinyu Niu, Dionisios N. Pnevmatikatos, Amit Kulkarni, Elias Vansteenkiste, Wayne Luk, Marco D. Santambrogio, Donatella Sciuto, Michael Hübner, Tobias Becker, Georgi Gaydadjiev, Antonis Nikitakis, Alex J. W. Thom
2016	B	`conf`	Liquid: Fast placement prototyping through steepest gradient descent movement. FPL Elias Vansteenkiste, Seppe Lenders, Dirk Stroobandt
2016	B	`conf`	Runtime-quality tradeoff in partitioning based multithreaded packing. FPL Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
2015	—	`conf`	Analyzing the divide between FPGA academic and commercial results. FPT Elias Vansteenkiste, Alireza Kaviani, Henri Fraisse
2015	—	`conf`	EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing. CSE Catalin Bogdan Ciobanu, Ana Lucia Varbanescu, Dionisios N. Pnevmatikatos, George Charitopoulos, Xinyu Niu, Wayne Luk, Marco D. Santambrogio, Donatella Sciuto, Muhammed Al Kadi, Michael Hübner, Tobias Becker, Georgi Gaydadjiev, Andreas Brokalakis, Antonis Nikitakis, Alex J. W. Thom, Elias Vansteenkiste, Dirk Stroobandt
2015	B	`conf`	Estimating circuit delays in FPGAs after technology mapping. FPL Berg Severens, Elias Vansteenkiste, Karel Heyse, Dirk Stroobandt
2015	J	`jnl`	FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. Microprocess. Microsystems Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Tobias Becker, Peter Böhm, Andreas Brokalakis, Karel Bruneel, Catalin Bogdan Ciobanu, Tom Davidson, Georgi Gaydadjiev, Karel Heyse, Wayne Luk, Xinyu Niu, Ioannis Papaefstathiou, Danilo Pau, Oliver Pell, Christian Pilato, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt, Tim Todman, Elias Vansteenkiste
2015	J	`jnl`	Identification of Dynamic Circuit Specialization Opportunities in RTL Code. ACM Trans. Reconfigurable Technol. Syst. Tom Davidson, Elias Vansteenkiste, Karel Heyse, Karel Bruneel, Dirk Stroobandt
2015	A	`conf`	Logic Gates in the routing network of FPGAs (Abstract Only). FPGA Elias Vansteenkiste, Berg Severens, Dirk Stroobandt
2014	—	`conf`	Parameterised FPGA reconfigurations for efficient test set generation. ReConFig Alexandra Kourfali, Elias Vansteenkiste, Dirk Stroobandt
2014	J	`jnl`	TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elias Vansteenkiste, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt
2013	—	`conf`	A connection-based router for FPGAs. FPT Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt
2013	—	`conf`	A novel tool flow for increased routing configuration similarity in multi-mode circuits. ISVLSI Brahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt
2013	B	`conf`	Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS. FPL Karel Heyse, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt
2012	—	`conf`	A Connection Router for the Dynamic Reconfiguration of FPGAs. ARC Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt
2012	B	`conf`	Maximizing the reuse of routing resources in a reconfiguration-aware connection router. FPL Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt