Elena Gramatová

21 papers A 1B 1C 14Journal 3Unranked 2

Year	Rank	Type	Title / Venue / Authors
2016	C	`conf`	A new method for path criticality calculation. DDECS Róbert Tamási, Miroslav Siebert, Elena Gramatová, Petr Fiser
2016	C	`conf`	A new user-friendly ATPG platform for digital circuits. DDECS Marek Lipovský, Ján Svarc, Elena Gramatová, Petr Fiser
2015	C	`conf`	Parameterized Critical Path Selection for Delay Fault Testing. DDECS Miroslav Siebert, Elena Gramatová
2013	C	`conf`	Delay Fault Coverage Increasing in Digital Circuits. DSD Miroslav Siebert, Elena Gramatová
2013	C	`conf`	Redundancy algorithm for embedded memories with block-based architecture. DDECS Stefan Kristofík, Elena Gramatová
2012	C	`conf`	D&T Presenter - electronic interactive system for design and test education. DDECS Matej Hlatký, Valter Martinek, Elena Gramatová
2011	J	`jnl`	A novel automatic test pattern generator for asynchronous sequential digital circuits. Microelectron. J. Roland Dobai, Elena Gramatová
2011	C	`conf`	Efficient diagnostics algorithms for regular computing structures. DDECS Miroslav Manik, Elena Gramatová
2010	C	`ed.`	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010 DDECS Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann
2010	J	`jnl`	Deductive Fault Simulation Technique for Asynchronous Circuits. Comput. Informatics Roland Dobai, Elena Gramatová
2010	C	`conf`	Test pattern generation for the combinational representation of asynchronous circuits. DDECS Roland Dobai, Elena Gramatová
2009	C	`conf`	Deductive Fault Simulation for Asynchronous Sequential Circuits. DSD Roland Dobai, Elena Gramatová
2009	C	`conf`	Diagnosis of faulty units in regular graphs under the PMC model. DDECS Miroslav Manik, Elena Gramatová
2008	C	`conf`	Boolean Formalisation of the PMC Model for Faulty Units Diagnosis in Regular Multi-Processor Systems. DDECS Miroslav Manik, Elena Gramatová
2007	C	`ed.`	Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007 DDECS Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino
2002	J	`jnl`	Hierarchical test generation for combinational circuits with real defects coverage. Microelectron. Reliab. T. Cibáková, Mária Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2002	C	`conf`	Integrated Design and Test Generation Under Internet Based Environment MOSCITO. DSD André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng
2002	A	`conf`	Internet-Based Collaborative Test Generation with MOSCITO. DATE André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová
2000	—	`conf`	Hierarchical defect-oriented fault simulation for digital circuits. ETW Mykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
1994	B	`conf`	The MD5 Message-Digest Algorithm in the XILINX FPGA. FPL P. Gramata, P. Trebaticky, Elena Gramatová
1993	—	`conf`	REGGEN-Test pattern generation on register transfer level. EURO-DAC Andrej Magdolen, Jana Bezakova, Elena Gramatová, Mária Fischerová