Elaheh Bozorgzadeh

56 papers A* 6A 10B 2C 3Misc 3Journal 22Unranked 10

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	AVERY: Adaptive VLM Split Computing through Embodied Self-Awareness for Efficient Disaster Response Systems. CoRR Rajat Bhattacharjya, Sing-Yao Wu, Hyunwoo Oh, Chaewon Nam, Suyeon Koo, Mohsen Imani, Elaheh Bozorgzadeh, Nikil D. Dutt
2014	—	`conf`	Distributed flow optimization control for energy-harvesting wireless sensor networks. ICC Kiyoshi Nakayama, Nga Dang, Lubomir F. Bic, Michael B. Dillencourt, Elaheh Bozorgzadeh, Nalini Venkatasubramanian
2012	C	`conf`	Adaptable intrusion detection using partial runtime reconfiguration. ICCD Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh
2012	J	`jnl`	Energy Harvesting for Sustainable Smart Spaces. Adv. Comput. Nga Dang, Elaheh Bozorgzadeh, Nalini Venkatasubramanian
2012	J	`jnl`	Hardware-Assisted Detection of Malicious Software in Embedded Systems. IEEE Embed. Syst. Lett. Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh
2012	—	`conf`	Minimization of Trojan footprint by reducing Delay/Area impact. DFT Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh
2012	J	`jnl`	QuARES: A quality-aware renewable energy-driven sensing framework. Sustain. Comput. Informatics Syst. Nga Dang, Elaheh Bozorgzadeh, Nalini Venkatasubramanian
2011	—	`conf`	QuARES: Quality-aware data collection in energy harvesting sensor networks. IGCC Nga Dang, Elaheh Bozorgzadeh, Nalini Venkatasubramanian
2011	J	`jnl`	SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shahin Golshan, Hessam Kooti, Elaheh Bozorgzadeh
2010	J	`jnl`	Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures. ACM Trans. Reconfigurable Technol. Syst. Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
2010	A	`conf`	Transition-aware real-time task scheduling for reconfigurable embedded systems. DATE Hessam Kooti, Elaheh Bozorgzadeh, Shenghui Liao, Lichun Bao
2009	J	`jnl`	Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations. IEEE Trans. Very Large Scale Integr. Syst. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2008	A	`conf`	Process variation aware system-level task allocation using stochastic ordering of delay distributions. ICCAD Love Singhal, Elaheh Bozorgzadeh
2008	C	`conf`	Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs. ICCD Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao
2008	J	`jnl`	Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh
2007	C	`conf`	Energy-aware co-processor selection for embedded processors on FPGAs. ICCD Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee
2007	Misc	`conf`	Heterogeneous Floorplanner for FPGA. FCCM Love Singhal, Elaheh Bozorgzadeh
2007	J	`jnl`	Interconnect Criticality-Driven Delay Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Love Singhal, Elaheh Bozorgzadeh, David Eppstein
2007	J	`jnl`	Multi-layer floorplanning for reconfigurable designs. IET Comput. Digit. Tech. Love Singhal, Elaheh Bozorgzadeh
2007	B	`conf`	Novel Multi-Layer floorplanning for Heterogeneous FPGAs. FPL Love Singhal, Elaheh Bozorgzadeh
2007	A*	`conf`	Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. DAC Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt, Juanjo Noguera
2007	A*	`conf`	Single-Event-Upset (SEU) Awareness in FPGA Routing. DAC Shahin Golshan, Elaheh Bozorgzadeh
2006	J	`jnl`	A Unified Theory of Timing Budget Management. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Soheil Ghiasi, Elaheh Bozorgzadeh, Po-Kuan Huang, Roozbeh Jafari, Majid Sarrafzadeh
2006	Misc	`conf`	CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures. FCCM Simin Dai, Elaheh Bozorgzadeh
2006	J	`jnl`	Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System. J. VLSI Signal Process. Soheil Ghiasi, Elaheh Bozorgzadeh, Karlene Nguyen, Majid Sarrafzadeh
2006	J	`jnl`	FABSYN: floorplan-aware bus architecture synthesis. IEEE Trans. Very Large Scale Integr. Syst. Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane
2006	J	`jnl`	Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. IEEE Trans. Very Large Scale Integr. Syst. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2006	—	`conf`	Minimizing peak power for application chains on architectures with partial dynamic reconfiguration. FPT Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
2006	B	`conf`	Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. FPL Love Singhal, Elaheh Bozorgzadeh
2006	—	`conf`	PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. ASP-DAC Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2006	A	`conf`	Physically-aware exploitation of component reuse in a partially reconfigurable architecture. IPDPS Love Singhal, Elaheh Bozorgzadeh
2006	J	`jnl`	Statistical Analysis and Design of HARP FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh
2005	J	`jnl`	A scheduling algorithm for optimization and early planning in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
2005	Misc	`conf`	Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. FCCM Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2005	A	`conf`	Fast timing closure by interconnect criticality driven delay relaxation. ICCAD Love Singhal, Elaheh Bozorgzadeh
2005	A*	`conf`	Floorplan-aware automated synthesis of bus-based communication architectures. DAC Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane
2005	A*	`conf`	Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. DAC Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
2004	A	`conf`	A unified theory of timing budget management. ICCAD Soheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh
2004	—	`conf`	Incremental Timing Budget Management in Programmable Systems. ERSA Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
2004	J	`jnl`	Optimal integer delay-budget assignment on directed acyclic graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
2004	J	`jnl`	Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs. J. Circuits Syst. Comput. Elaheh Bozorgzadeh, Seda Ogrenci Memik, Xiaojian Yang, Majid Sarrafzadeh
2003	J	`jnl`	Creating and exploiting flexibility in rectilinear Steiner trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
2003	A	`conf`	Customized regular channel design in FPGAs. FPGA Elaheh Bozorgzadeh, Majid Sarrafzadeh
2003	A	`conf`	On computation and resource management in an FPGA-based computation environment. FPGA Soheil Ghiasi, Karlene Nguyen, Elaheh Bozorgzadeh, Majid Sarrafzadeh
2003	A*	`conf`	Optimal integer delay budgeting on directed acyclic graphs. DAC Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
2002	J	`jnl`	Budget Management with Applications. Algorithmica Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh
2002	J	`jnl`	Instruction generation for hybrid reconfigurable systems. ACM Trans. Design Autom. Electr. Syst. Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh
2002	J	`jnl`	Pattern routing: use and theory for increasing predictability andavoiding coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
2001	A	`conf`	A Super-Scheduler for Embedded Reconfigurable Systems. ICCAD Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
2001	—	`conf`	An exact algorithm for coupling-free routing. ISPD Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
2001	A*	`conf`	Creating and Exploiting Flexibility in Steiner Trees. DAC Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
2001	—	`conf`	Design and analysis of physical design algorithms. ISPD Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava
2001	A	`conf`	Instruction Generation for Hybrid Reconfigurable Systems. ICCAD Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh
2001	—	`conf`	RPack: routability-driven packing for cluster-based FPGAs. ASP-DAC Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh
2001	—	`conf`	Wirelength estimation based on rent exponents of partitioning and placement. SLIP Xiaojian Yang, Elaheh Bozorgzadeh, Majid Sarrafzadeh
2000	A	`conf`	Predictable Routing. ICCAD Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh